MT29F8G08ABABAWP-IT:B Micron Technology Inc, MT29F8G08ABABAWP-IT:B Datasheet
MT29F8G08ABABAWP-IT:B
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MT29F8G08ABABAWP-IT:B Summary of contents
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... Erase Block: 700µs (TYP) • Operating Voltage Range – Vcc: 2.7–3.6V – VccQ: 1.7–1.95V, 2.7–3.6V • Command set: ONFI NAND Flash Protocol • Advanced Command Set – Program Cache – Read Cache Sequential – Read Cache Random – ...
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... Part Numbering Information Micron NAND Flash devices are available in different configurations and densities (see Figure 1). Figure 1: Marketing Part Number Chart MT 29F 8G 08 Micron Technology Single-Supply NAND Flash 29F = Single-supply NAND Flash memory Density 8G = 8Gb Device Width bits Level Bit/Cell A 1-bit Classification ...
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... READ PAGE (00h–30h .64 READ PAGE CACHE SEQUENTIAL (31h .65 PDF: 09005aef8386131b/Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. 1.0 2/09 EN Micron Confidential and Proprietary 8Gb Asynchronous/Synchronous NAND Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. 3 Advance Table of Contents ©2008 Micron Technology, Inc. All rights reserved. ...
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... Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Revision History 142 PDF: 09005aef8386131b/Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. 1.0 2/09 EN Micron Confidential and Proprietary 8Gb Asynchronous/Synchronous NAND Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. 4 Advance Table of Contents ©2008 Micron Technology, Inc. All rights reserved. ...
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... Pin Assignment (Top View) 48-Pin TSOP Type Figure 3: Pad Assignment (Top View) 52-Pad LGA .10 Figure 4: Ball Assignment – 100-Ball VBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Figure 5: NAND Flash LUN Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Figure 6: Device Organization for Single-Die Package (TSOP/BGA .14 Figure 7: Device Organization for Single-Die Package (LGA .14 Figure 9: Asynchronous COMMAND LATCH Cycle ...
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... Figure 107: 52-Pad ULGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Figure 108: 100-Ball VBGA (Package Code H1), 12×18 141 PDF: 09005aef8386131b/Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. 1.0 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. 6 Advance List of Figures ...
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... Valid Blocks per LUN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Table 39: Array Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 PDF: 09005aef8386131b/Source: 09005aef838cad98 m61a_ascyn_sync_nand.fm - Rev. 1.0 2/09 EN Micron Confidential and Proprietary 8Gb Asynchronous/Synchronous NAND Flash Memory Q = 1.7–1.95V .89 CC Micron Technology, Inc., reserves the right to change products or specifications without notice. 7 Advance List of Tables ...
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... Data transfers in the synchronous interface include a bidirectional data strobe (DQS). Between the synchronous and asynchronous interfaces there are five control signals used to implement the NAND Flash protocol. In the synchronous interface these signals are CE#, CLE, ALE, CLK, and W/R#; in the asyn- chronous interface these signals are CE#, CLE, ALE, WE#, and RE# ...
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... For synchronous devices with VccQ = 1.8V, these signals must be supplied with a 1.8V volt- age supply. 4. Signal names in parentheses are the signal names when the synchronous interface is active. PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory ...
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... Pad Assignment (Top View) 52-Pad LGA Notes: 1. These pads are currently NC and are shown for future placement 2. These pads are currently NC and are shown for future placement PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory CE4 CLE-1 CE3# ...
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... N/A: This signal is tri-stated when the asynchronous interface is active. 2. Signal names in parentheses are the signal names when the synchronous interface is active. 3. These pads are currently NC and are shown for future placement. PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory ...
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... When the synchronous interface is active, W/R# controls the direction of DQ[7:0] and DQS. Input Write enable and clock: WE# transfers commands, addresses, and serial data from the host system to the NAND Flash when the asynchronous interface is active. When the synchronous interface is active, CLK latches command and address cycles. Input Write protect: WP signal that enables or disables array PROGRAM and ERASE operations ...
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... The addresses are latched by an address register and sent to a row decoder to select a row address column decoder to select a column address. Data is transferred to or from the NAND Flash memory array, byte-by-byte, through a data register and a cache register. See Figure 5 for details. ...
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... Addressing and Memory Map NAND Flash devices do not contain dedicated address pins. Addresses are loaded using a 5-cycle sequence shown in Table 2 on page 23. Device and Array Organization Figure 6: Device Organization for Single-Die Package (TSOP/BGA) CLE (CLE-1) ALE (ALE-1) RE# (W/R#) I/O[7:0] (DQ[7:0]) WP# (WP#-1) Notes: 1 ...
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... BA[8] is the plane-select bit: Plane 0: BA[7] = "0" Plane 1: BA[7] = "1" PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory Logical Unit (LUN) 4,320 bytes 4,320 bytes 4,096 4,096 224 ...
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... LOW, all of the signals for that target are enabled. With CE# LOW, the target can accept commands, addresses, and data I/O. There may be more than one target in a NAND Flash package. Each target is controlled by its own CE#; the first target is controlled by CE#; the second target (if present) is controlled by CE2#, etc. ...
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... Addresses are typically ignored by LUNs that are busy; however, some addresses are accepted by LUNs even when they are busy; for example, like address cycles that follow the SELECT LUN WITH STATUS (78h) command. PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory t CLS t CLH ...
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... RE# is HIGH. Data input is ignored by LUNs that are not selected or are busy, except if the LUN is busy with a PROGRAM PAGE CACHE MODE operation. PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory t CLS ALS ...
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... I/Ox, DQx Asynchronous Data Output Data can be output from a LUN READY state. Data output is supported following a READ operation from the NAND Flash array. Data is output from the cache register of the selected LUN to I/O[7:0], DQ[7:0] on the falling edge of RE# when: • CE# is LOW, • ...
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... RP RE# I/ R/B# Figure 13: Asynchronous Data Output Cycles (EDO Mode) CE# RE# I/Ox, DQx t RR RDY PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory t REA t REH t RHZ D D OUT OUT REH t REA t REA t RLOH ...
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... The minimum value for Rp is determined by the output drive capability of the R/B# signal, the output voltage swing, and VCCQ. Where Σ IL PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory × (resistance of pull-up resistor), and C ...
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... Rise primarily dependent on external pull-up resistor and external capacitive loading Fall =10ns at 3.3V 5. See TC values in Figure 19 on page 24 for approximate Rp value and TC. PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory controller R/B# Open drain output ...
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... Figure 17: IOL vs 3.3V) CC 3.50 3.00 2.50 2.00 I(mA) 1.50 1.00 0.50 0.00 PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory Q = 1.8V) t Fall t Rise - Rise are calculated at 10 percent and 90 percent points. 0 2000 4000 ...
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... I (mA) 1.50 1.00 0.50 0.00 Figure 19: TC vs. Rp 1200 1000 T(ns) PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory 0 2,000 4,000 6,000 Rp (Ω) 800 600 400 200 Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... Existing signals are redefined for high-speed DDR I/O. The WE# signal becomes CLK. DQS is enabled. The RE# signal becomes W/R#. CLK provides a clock reference to the NAND Flash device. DQS is a bidirectional data strobe. During data output, DQS is driven by the NAND Flash device. During data input, DQS is controlled by the host controller while inputting data on DQ[7:0]. ...
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... During data input to the device, DQS is the “clock” that latches the data in the cache regis- ter. 5. During data output from the NAND Flash device, DQS is an output generated from CLK after 6. Mode selection settings for this table Logic level HIGH Logic level LOW ...
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... SELECT LUN WITH STATUS (78h) to prevent data output contention. PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory t CALS t DQSD Bus driving Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... DQS DQ[7:0] Notes: 1. When CE# remains LOW, mand cycle is latched for subsequent command, address, data input, or data output cycle(s). PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory t t CK, is greater than CAD CALS t CALS ...
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... DQS DQ[7:0] Notes: 1. When CE# remains LOW, mand cycle is latched for subsequent command, address, data input, or data output cycle(s). PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory t t CK, is greater than CAD CALS t CAD ...
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... Data input is ignored by LUNs that are not selected or are busy. PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory t WPST, the bus enters bus idle mode and t CAD starts, the host can disable the target if desired. ...
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... When CE# remains LOW, pletes DSH (MIN) generally occurs during t 3. DSS (MIN) generally occurs during PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory t CALS t CAD t CALS t DQSS t DSH t DSS t DSH t WPRE t DQSH t DQSL ...
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... Synchronous DDR Data Output Data can be output from a LUN ready. Data output is supported following a READ operation from the NAND Flash array. To enter the DDR data output mode, the following conditions must be met: • CLK is running, • CE# is LOW, • The host has released the DQ[7:0] bus and DQS, • ...
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... For W/R# transitioning LOW: DQ[7:0] drives current state and DQS goes LOW. 6. After final data output, DQ[7:0] is driven until W/R# goes HIGH, but is not valid. PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory t CALS t CALS ...
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... Ready/Busy# See “Ready/Busy# (R/B#)” on page 21 under “Asynchronous Interface”. PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. 34 Advance Bus Operation ©2008 Micron Technology, Inc. All rights reserved. ...
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... RESET (FFh) command is issued. 6. The RESET (FFh) command must be the first command issued to all targets (CE#s) after the NAND Flash device is powered on. Each target will be busy for a maximum of t POR after a RESET command is issued. The RESET busy time can be monitored by polling R/B# or issuing the READ STATUS (70h) command to poll the status register ...
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... R/B# Vcc ramp starts PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory 10μs (MAX) 100μs (MAX) Micron Technology, Inc., reserves the right to change products or specifications without notice. 36 Advance Vcc Power Cycling ...
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... Each target's interface is independent of other targets, so the host is responsible for changing the interface for each target. If the host and NAND Flash device, through error, are no longer using the same interface, then steps under "Activating the Asynchronous Interface" are performed to resynchro- nize the interfaces. ...
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... Figure 27: Activating the Synchronous Interface Cycle Type DQx SR[6] Notes Timing mode. PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory CMD ADDR DIN DIN DIN t ADL EFh 01h Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... ERASE BLOCK 60h ERASE BLOCK MULTI-PLANE 60h COPYBACK Operations COPYBACK READ 00h 85h COPYBACK PROGRAM PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory # Valid Data Address Input Command Cycles Cycles Cycle #2 0 — 0 — ...
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... ARDY = "0") is supported if the previous command was a PROGRAM PAGE CACHE (80h-15h) command; otherwise it is prohibited. 8. Command cycle #2 of 11h is conditional. See “CHANGE ROW ADDRESS (85h)” for more details. PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory # Valid Data Address Input Command Cycles ...
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... I/Ox (DQx) FFh RESET command PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory t RST, the host can poll each LUN's status register RST Micron Technology, Inc., reserves the right to change products or specifications without notice. 41 ...
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... SYNCHRONOUS RESET (FCh) Cycle CE# CLE ALE CLK W/R# DQS DQ[7:0] R/B# PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory t RST, the host can poll each LUN's status register CALS t CALH t CALS t CALH t CAD t CALH t WB ...
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... READ ID Parameters for Address 00h Options Byte 0 − Manufacturer ID Manufacturer Micron Byte 1 − Device ID Vcc 3.3V PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory Command Address D t WHR 90h 00h Byte 0 Command Address ...
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... Writing ECh to the command register puts the target in read parameter page mode. The target stays in this mode until another valid command is issued. PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory I/O7 I/O6 I/O5 I/O4 ...
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... READ PARAMETER PAGE (ECh) Operation Cycle type Command Address I/O[7:0] (DQ[7:0]) ECh R/B# PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory D D OUT 00h Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... Read Parameter Page. PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory Device MT29F8G08CBABA MT29F8G08CBCBB MT29F8G08ABABAWP MT29F8G08ABCBBWP MT29F8G08ABABAC3 MT29F8G08ABCBBH1 Micron Technology, Inc., reserves the right to change products or specifications without notice. 46 Advance Command Definitions Values – ...
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... Electrical parameters block 128 I/O pin capacitance per chip enable PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory Device Micron Technology, Inc., reserves the right to change products or specifications without notice. 47 Advance Command Definitions Values – ...
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... MT29F8G08ABABA MT29F8G08ABCBB MT29F8G08ABABAWP MT29F8G08ABABAC3 MT29F8G08ABCBBWP MT29F8G08ABCBBH1 MT29F8G08ABABAWP MT29F8G08ABABAC3 MT29F8G08ABCBBWP MT29F8G08ABCBBH1 MT29F8G08ABABAWP MT29F8G08ABABAC3 MT29F8G08ABCBBWP MT29F8G08ABCBBH1 MT29F8G08ABABAWP MT29F8G08ABABAC3 MT29F8G08ABCBBWP MT29F8G08ABCBBH1 Micron Technology, Inc., reserves the right to change products or specifications without notice. 48 Advance Command Definitions Values – 1Fh, 00h – 1Fh, 00h – F4h, 01h – ...
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... Bit Supports Get/Set Features command set Bit Does not support A5h/A0h/AFh OTP command set PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory Device Micron Technology, Inc., reserves the right to change products or specifications without notice. 49 Advance Command Definitions Values – ...
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... Reserved (FFh) 4,319 PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory Device MT29F8G08ABABAWP MT29F8G08ABABAC3 MT29F8G08ABCBBWP MT29F8G08ABCBBH1 Micron Technology, Inc., reserves the right to change products or specifications without notice. 50 Advance Command Definitions Values – ...
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... Figure 33: READ UNIQUE ID (EDh) Operation Cycle type Command Address I/O[7:0] (DQ[7:0]) EDh R/B# PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory D D OUT 00h Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... Feature address 01h (timing mode) operation is unique. If SET FEATURES is used to modify the interface type, the target will be busy for page 37 for details. PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory Reserved Timing mode Reserved Programmable output drive strength Reserved ...
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... When the synchronous interface is active, two data bytes are output per toggle, one byte for each rising or falling edge of DQS. Figure 35: GET FEATURES (EEh) Operation Cycle type I/Ox (DQx) R/B# PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory Address ADL FA P1 ...
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... Nominal (default) Underdrive Reserved P2 Reserved P3 Reserved P4 Reserved Notes: 1. See “Output Drive Strength” on page 89 for details. PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory I/O7 I/O6 I/O5 I/O4 (DQ7) (DQ6) (DQ5) (DQ4) (DQ3 ...
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... OTP Block Reserved P2 Reserved P3 Reserved P4 Reserved Notes: 1. See “One-Time Programmable (OTP) Operations” on page 82 for details. PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory I/O7 I/O6 I/O5 I/O4 I/O3 (DQ7) (DQ6) (DQ5) (DQ4) (DQ3 ...
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... I/O[7:0], DQ[7:0] as long as CE# and W/R# are LOW and ALE and CLE are HIGH. DQS also toggles while ALE and CLE are HIGH. While monitoring the status register to determine when a data transfer from the Flash array to the data register ( command to disable the status register and enable data output (see READ MODE 00h on page 55) ...
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... LUN on a target even when it is busy (RDY = 0). This command is accepted by all LUNs, even when they are BUSY (RDY = 0). PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory 1 Pass/Fail (N-1): "0" = Pass "1" = Fail This bit is set if the previous operation on the selected LUN failed. This bit is valid only when RDY (SR bit 6) is " ...
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... RESET, identification, and configuration operations. See individual operations for specific details. Figure 37: SELECT LUN WITH STATUS (78h) Operation Cycle type I/Ox (DQx) PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory Command Address Address Address t WHR 78h Micron Technology, Inc ...
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... After the E0h command cycle is issued, the host must wait at least data output mode until another valid command is issued. PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory D Command Address Address Command ...
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... In devices that have more than one LUN per target, the CHANGE WRITE COLUMN (85h) command can be used with other commands that support multi-LUN operations. PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory Address Address Address Address ...
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... CHANGE ROW ADDRESS (85h) The CHANGE ROW ADDRESS (85h) command changes the row address (block and page) where the cache register contents will be programmed in the NAND Flash array. It also changes the column address of the selected cache register and enables data input on the specified LUN. This command is accepted by the selected LUN when it is ready (RDY = 1 ...
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... READ Operations READ operations are used to copy data from the NAND Flash array of one or more of the planes to their respective cache registers, and to enable data output from the cache registers to the host through the DQ bus. ...
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... After RCBSY, R/B# goes HIGH, RDY = 1 and ARDY = 0, indicating that the cache register is available for data output and that the specified page is copying from the NAND Flash array to the data register. Data can then be output from the cache register, beginning at column address 0. The CHANGE READ COLUMN (05h-E0h) command can be used to change the column address of the data being output by the cache register ...
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... LUN prior to issuing the READ MODE (00h) command. This prevents bus conten- tion. READ PAGE (00h–30h) The READ PAGE (00h–30h) command copies a page from the NAND Flash array to its respective cache register and enables data output. This command is accepted by the LUN when it is ready (RDY = 1, ARDY = 1). ...
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... R/B# goes HIGH and the LUN is busy with a cache operation (RDY = 1, ARDY = 0), indicating that the cache register is available and that the specified page is copying from the NAND Flash array to the data register. 3. Data can be output from the cache register, beginning at column address 0. The CHANGE READ COLUMN (05h-E0h) command can be used to change the column address of the data being output from the cache register ...
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... R/B# goes HIGH and the LUN is busy with a cache operation (RDY = 1, ARDY = 0), indicating that the cache register is available and that the specified page is copying from the NAND Flash array to the data register. 3. Data can be output from the cache register beginning at column address 0. The CHANGE READ COLUMN (05h-E0h) command can be used to change the column address of the data being output from the cache register ...
Page 67
... The READ PAGE MULTI-PLANE (00h-32h) can be used to setup multi-plane cache read operations. The READ PAGE MULTI-PLANE (00h-32h) command queues a plane to transfer data from the NAND flash array to its cache register. This command can be issued one or more times. Each time a new plane address is specified, that pane is also queued for data transfer ...
Page 68
... Additional READ PAGE MULTI-PLANE (00h-32h) commands can be issued to queue additional planes for data transfer. 4. The READ PAGE (00h-30h) command is issued. 5. Data is transferred from the NAND Flash array for all of the addressed planes to their respective cache registers. 6. When the LUN is ready (RDY = 1, ARDY = 1), data output is enabled for the cache reg- ister linked to the even plane ...
Page 69
... READ PAGE MULTI-PLANE (00h–32h) The READ PAGE MULTI-PLANE (00h-32h) command queues a plane to transfer data from the NAND flash array to its cache register. This command can be issued one or more times. Each time a new plane address is specified, that plane is also queued for data transfer ...
Page 70
... Additional READ PAGE MULTI-PLANE (00h-32h) commands can be issued to queue additional planes for data transfer. 4. The READ PAGE (00h-30h) command is issued. 5. Data is transferred from the NAND Flash array for all of the addressed planes to their respective cache registers. 6. When the LUN is ready (RDY = 1, ARDY = 1), data output is enabled for the cache reg- ister linked to the even plane ...
Page 71
... The PROGRAM PAGE (80h-10h) command, when not preceded by the PROGRAM PAGE MULTI-PLANE (80h-11h) command, programs one page from the cache register to the NAND Flash array. When the LUN is ready (RDY = 1, ARDY = 1), the host should check the FAIL bit to verify that the operation has completed successfully. ...
Page 72
... A page is input to the cache register and moved to the NAND Flash array at the block and page address specified. 3. Five address cycles containing the column address and row address are written to the address register ...
Page 73
... MULTI-PLANE (80h-11h) commands. Data for all of the addressed planes is trans- ferred from the cache registers to the corresponding data registers, then moved to the NAND Flash array. The host should check the status of the operation by using the sta- tus operations (70h, 78h). See“Multi-Plane Addressing” on page 86 for multi-plane addressing requirements ...
Page 74
... The PROGRAM PAGE MULTI-PLANE (80h-11h) command enables the host to input data to the addressed plane's cache register and queue the cache register to ultimately be moved to the NAND Flash array. This command can be issued one or more times. Each time a new plane address is specified that plane is also queued for data transfer. To input ...
Page 75
... CACHE (80h-15h) command. All of the queued planes will move the data to the NAND Flash array. This command is accepted by the LUN when it is ready (RDY = 1). To input a page to the cache register and queue moved to the NAND Flash array at the block and page address specified, write 80h to the command register. Unless this ...
Page 76
... ERASE Operations ERASE operations are used to clear the contents of a block in the NAND Flash array to prepare its pages for program operations. ERASE Operations The ERASE BLOCK (60h-D0h) command, when not preceded by the ERASE BLOCK MULTI-PLANE (60h-D1h) command, erases one block in the NAND Flash array. When the LUN is ready (RDY = 1, ARDY = 1), the host should check the FAIL bit to verify that this operation completed successfully ...
Page 77
... ERASE BLOCK MULTI-PLANE (60h–D1h) The ERASE BLOCK MULTI-PLANE (60h-D1h) command queues a block in the specified plane to be erased in the NAND Flash array. This command can be issued one or more times. Each time a new plane address is specified, that plane is also queued for a block to be erased ...
Page 78
... The COPYBACK PROGRAM MULTI-PLANE (85h-11h) command can be used to improve system performance of COPYBACK PROGRAM operations by enabling movement of multiple pages from the cache registers to different planes of the NAND Flash array. This is done by prepending one or more COPYBACK PROGRAM (85h-11h) commands in front of the COPYBACK PROGRAM (85h-10h) command. ...
Page 79
... PROGRAM PAGE (80h-10h) command, except that when 85h is written to the command register, cache register contents are not cleared. See “PROGRAM PAGE (80h–10h)” on page 72 for further details. PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory Address Address Address Address C2 ...
Page 80
... PROGRAM PAGE MULTI-PLANE (85h-11h) command, except that when 85h is written to the command register, cache register contents are not cleared. See "PROGRAM PAGE MULTI-PLANE 80h-11h" on page 63 for further details. PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory Address Address Address Address C2 ...
Page 81
... Cycle type Command Address Address I/O[7:0] 85h C1 C2 (DQ[7:0]) RDY PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory Address Address Address ADL Micron Technology, Inc., reserves the right to change products or specifications without notice. 81 ...
Page 82
... In Micron NAND Flash devices, the OTP area leaves the factory in an erased state (all bits are "1"). Programming enables the user to program only "0" bits in the OTP area. The OTP area cannot be erased, even not protected ...
Page 83
... Cycle type Command Address Address Address I/O[7:0] 80h C1 C2 OTP Page (DQ[7:0]) R/B# PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory t t OBSY. After OBSY, the status register is set to 60h. Address Address ADL 00h ...
Page 84
... When the device is ready, read the FAIL bit of the status register to determine if the oper- ation passed or failed (see Table 14 on page 56). PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory Address Address Address t ADL ...
Page 85
... Figure 60: READ OTP PAGE (00h–30h) Operation Cycle type Command Address I/O[7:0] 00h C1 (DQ[7:0]) R/B# PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory Address Address Address ADL 01h 00h 00h 00h data is transferred. ...
Page 86
... Multi-Plane Operations Each NAND Flash logical unit (LUN) is divided into multiple physical planes. Each plane contains a cache register and a data register independent of the other planes. The planes are addressed via the low-order block address bits. Specific details are provided in Figure 8 and Table 2 on page 13. ...
Page 87
... PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. 87 Advance Multi-LUN Operations © ...
Page 88
... Error Management Each NAND Flash LUN is specified to have a minimum number of valid blocks (NVB) of the total available blocks. This means the LUNs could have blocks that are invalid when shipped from the factory. An invalid block is one that contains at least one page that has more bad bits than can be corrected by the minimum required ECC ...
Page 89
... Output Drive Strength Because High Speed NAND Flash is designed for use in systems that are typically point- to-point connections, an option to control the drive strength of the output buffers is provided. Drive strength should be selected based on the expected loading of the memory bus. There are four supported settings for the output drivers - overdrive 2, over- drive 1, nominal, and underdrive ...
Page 90
... Mismatch is the absolute value between pull-up and pull-down impedances. Both are mea- sured at the same temperature and voltage. 2. Test conditions: VccQ = VccQ(min), Vout = VccQ × 0.5. PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory Process Fast-Fast Typical-Typical Slow-Slow Rpd/Rpu ...
Page 91
... Maximum overshoot are above V Maximum undershoot area below Figure 61: Overshoot Figure 62: Undershoot PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory Synchronous AC Overshoot/Undershoot Specifications 0 (50ns) (30ns Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
Page 92
... Temperature Range Table 25: Output Slew Rate (VccQ = 1.7–1.95V) Output Drive Strength Overdrive 2 Overdrive 1 Nominal Underdrive PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory Timing Mode 0 1 0.5 0.5 TBD TBD TBD TBD ) LOAD Micron Technology, Inc ...
Page 93
... I/O burst read current RC = I/O burst write current Bus idle current Standby current (CMOS) Notes: 1. All values are per LUN unless otherwise specified. PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory Symbol STG ...
Page 94
... Cin/Cout (I/O[7:0], DQ[7:0]) Notes: 1. These parameters are verified in device characterization and are not 100 percent tested.Test conditions SDP = Single die package.. PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory Conditions Symbol (MIN) I 1_s ...
Page 95
... Notes: 1. Transmission line delay is assumed to be very small. 2. This test setup applies to all package configurations. PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory 2 Device SDP SDP = 25° MHz 0V. IN ...
Page 96
... DC characteristics may need to be relaxed if R/B# pull-down strength is not set to “Full.” See Table 13 on page 14 for additional details. PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory Symbol Min Typ VIH (AC) 0.8 × ...
Page 97
... Output leakage current Output low current (R/B#) Notes: 1. The DC values only apply to the synchronous interface All leakage currents are per LUN. PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory Condition Symbol Min V (AC) 0.8 × ...
Page 98
... DQS input low pulse DQSL width t DQS-DQ skew DQSQ t Data input DQSS 0.75 t Data In setup DS PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory Mode 0 Mode 1 Mode 2 Max Min Max Min Max ≈20 ≈33 ≈50 – ...
Page 99
... If RESET (FFh) is issued when the target is idle, the target goes busy for a maximum of 5µs. Table 37: AC Characteristics: Asynchronous Command, Address, and Data Parameter Symbol Clock Period PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory Mode 0 Mode 1 Mode 2 Max Min Max Min Max 0.2 – ...
Page 100
... WE# high WH hold time t WE# high to WHR RE# low t WE# pulse width WP PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory Mode 0 Mode 1 Mode 2 Min Max Min Max Min Max ≈10 ≈20 ≈28 200 – ...
Page 101
... SELECT LUN WITH STATUS (78h), is prohibited LPROG = address load time (last page) - data load time (last page). PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory Mode 0 Mode 1 Mode 2 Min Max Min Max Min ...
Page 102
... The cycle that tCAD is measured from may be an idle cycle (as shown), another command cycle, and address cycle data cycle. The idle cycle is shown in this diagram for simplicity. PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory t CALS t CAD t DQSS Feat ...
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... DQS 00h DQx 90h or 20h PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory t WHR t CALS t DQSD t DQSCK Byte 0 Byte 0 Byte 1 Byte 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. 103 ...
Page 104
... W/R# DQS Feat DQx EEh Addr R/B# PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory t CALS t WRCK t CALS t DQSD t DQSCK FEAT Micron Technology, Inc., reserves the right to change products or specifications without notice. 104 ...
Page 105
... ALE CLK W/R# DQS DQx R/B# PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory t WHR t CAD t DQSD 70h READ STATUS command Micron Technology, Inc., reserves the right to change products or specifications without notice. 105 ...
Page 106
... ALE t CAD t CAD CLK W/R# DQS DQx 78h PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory t CAD t CAD t WHR t CAD Row Row Row add 1 add 2 add 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
Page 107
... CAD t CAD CLK W/R# DQS DQx ECh R/B# PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory t CALS t WRCK t DQSD t DQSCK 00h Micron Technology, Inc., reserves the right to change products or specifications without notice. 107 ...
Page 108
... CAD CLK t CALS W/R# DQS Row DQx 30h add R/B# 1 PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory t CAD t CAD t CAD t CAD Col Col Row add 1 add 2 add 1 t CALS t WRCK t DQSD t DQSCK ...
Page 109
... DQS Col 05h DQx add 1 R/B# PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory t CALS t CAD t CCS t DQSD t DQSCK Col E0h add 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
Page 110
... R/B# Initial Read Sequential Access Read Access A PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory t DQSHZ t DQSD t DQSCK Initial Read Data Data Output Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
Page 111
... DQSD t DQSCK DQS DQx t RCBSY R/B# 1 PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory t RHW t DQSHZ Sequential Read Data A 3Fh Data Output RCBSY Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
Page 112
... Cycles R/B# Initial Read Access PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory t DQSD t DQSCK 31h RCBSY Random Read Access A Micron Technology, Inc., reserves the right to change products or specifications without notice. 112 ...
Page 113
... DQx RCBSY R/B# Random Read Access B 1 PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory t RHW t DQSHZ t DQSCK Random Read Data A 3Fh Data Output RCBSY Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
Page 114
... Cycles or 00h RDY PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory t CALS t CAD CAD If data from a plane other than A is desired, a 06h-E0h command sequence is required after t R and prior to taking W/R# low. Address B ...
Page 115
... ALE t RHW CLK t DQSHZ W/R# t DQSCK DQS Data A DQx Output RDY 3 PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory t RHW t CAD t DQSHZ Data B Address A 06h Output t CAD t CAD CCS Address B 06h E0h 5 Cycles Micron Technology, Inc ...
Page 116
... ALE t CAD t CAD CLK W/R# DQS Col DQx 80h add 1 R/B# PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory t CALS t CAD t CAD t CAD t CAD Col Row Row Row add 2 add 1 add 2 add 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
Page 117
... DQx N N+1 M-2 M-1 M R/B# 1 PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory t CAD PROG t CAD 10h 70h READ STATUS command Micron Technology, Inc., reserves the right to change products or specifications without notice. 117 ...
Page 118
... CLE ALE t CAD t CAD t CAD CLK W/R# DQS Col DQx 85h add 1 R/B# PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory t CAD t CAD Col 85h add 1 t CALS t CCS t DQSS Col add 2 C C+1 1 Micron Technology, Inc ...
Page 119
... Address B DQx Data B 5 Cycles RDY 1 PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory t CALS t DQSS Data A t CAD PROG 10h 70h Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
Page 120
... CAD CLK W/R# DQS Row DQx 60h add 1 R/B# PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory t CAD t CAD Row Row D0h add 2 add 3 READ STATUS BERS command Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
Page 121
... Address DQx 00h or 30h Cycles R/B# PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory t DQSD t DQSCK Micron Technology, Inc., reserves the right to change products or specifications without notice. 121 Advance Timing Diagrams t CADx2 ...
Page 122
... W/R# t DQSD t DQSCK DQS h DQx R/B# 1 PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory t CAD t RHW t CAD DQSHZ 5 Address Data 85h 85h Cycles Output Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
Page 123
... CAD CLK W/R# DQS DQx R/B# 2 PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory PROG t WHR t CAD 10h 70h Micron Technology, Inc., reserves the right to change products or specifications without notice. 123 Timing Diagrams ...
Page 124
... CAD CLK W/R# DQS Col Col DQx 00h add 1 add 2 R/B# PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory t CAD t CAD t CAD t CAD t CALS OTP 30h 00h 00h page Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... CAD CLK W/R# DQS Col DQx 80h add 1 R/B# PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory t CAD t CAD t CAD t CAD Col OTP 00h 00h add 2 page 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... IN DQx M-2 M-1 M R/B# 1 PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory t CAD PROG t CAD 10h 70h READ STATUS command Don’t Care Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... CLE t CALS ALE CAD CLK W/R# DQS DQx 10h R/B# 1 PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory t CAD t CAD t CAD t CAD Col Col 01h 00h 00h t PROG t WHR t CAD t DQSD 70h READ STATUS command Micron Technology, Inc ...
Page 128
... FFh I/Ox (DQx) RESET command Figure 89: READ STATUS Cycle CLE CE# WE# RE# I/Ox (DQx) PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory RST t CLR t CLS t CLH WHR 70h Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... I/Ox (DQx) 78h Figure 91: READ PARAMETER PAGE CLE WE# ALE RE# I/Ox (DQx) ECh 00h R/B# PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory ALH t ALS Row add 1 Row add 2 Row add Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... ALE RE# Col I/Ox (DQx) 00h add 1 RDY PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory Col Row Row Row 30h add 2 add 1 add 2 add 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
Page 131
... Address (5 cycles) Figure 94: CHANGE READ COLUMN CLE CE# WE# ALE RE# I/Ox (DQx) RDY PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory t R 30h t CEA CE# t REA t CHZ t COH RE# Out I/Ox t RHW t RC Col ...
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... REA t DS DOUT DOUT I/Ox 31h DOUT 0 1 Page address M R/B# Column address 0 1 PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory Row Row 30h 31h add 2 add 3 Page address RHW t CEA REA ...
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... I/Ox Column address Page address 00h N R/B# 1 PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory Row Row Row 30h add 1 add 2 add 3 Page address M t CLS t CLH t CS ...
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... PROGRAM PAGE Operation CLE CE WE# ALE RE# Col Col I/Ox (DQx) 80h add 1 add 2 RDY PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory WHR t REA 1 Byte 1 Byte 0 t ADL Row Row Row add 1 add 2 ...
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... ALE RE# I/Ox Col Col Row Row Row 80h (DQx) add 1 add 2 add 1 add 2 add 3 RDY PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory Data input CE WE# t ADL t CCS D D Col Col IN IN 85h M N ...
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... D IN 80h (DQx) add 1 add 2 add 1 add 2 add 3 N Serial input Last page – 1 PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory CBSY IN D Col Col IN 15h 80h N M add 1 add 2 Serial input ...
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... WC WE# ALE RE# I/Ox Row Row 60h add 1 add 2 (DQx) Row address RDY PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory 35h Col Col Row 85h (or 30h) add 1 add 2 add 1 add 2 Busy BERS Row ...
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... Notes: 1. All dimensions are in millimeters. PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory 20.00 ±0.25 18.40 ±0.08 See detail A 1.20 MAX Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... Notes: 1. All dimensions are in millimeters. PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory 0.25 for reference only 0.50 for reference only 48 25 See detail A 1.20 MAX 0.10 Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... Primary datum A (seating plane) is defined by the bottom terminal surface. Metallized test terminal lands or interconnect terminals need not extend below the package bottom sur- face. PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory 6.00 4.00 Pad A1 2.00 3.00 Ø ...
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... Dimensions apply to solder balls post-reflow. Pre-reflow balls are Ø0.42 on Ø0 SMD ball pads TYP 1 TYP 1 TYP Notes: 1. All dimensions in PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory 0.64 ±0.05 6 ±0.05 Ball ±0. ±0 ...
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... Initial release • PDF: 09005aef8386131b / Source: 09005aef838cad98 m61a_async_sync_nand.fm - Rev. A 2/09 EN Micron Confidential and Proprietary 8Gb Asychronous/Synchronous NAND Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. 142 Advance Revision History ©2008 Micron Technology, Inc. All rights reserved. ...