MT29F8G08ABABAWP-IT:B Micron Technology Inc, MT29F8G08ABABAWP-IT:B Datasheet - Page 16

• Manufacturer Part Number: MT29F8G08ABABAWP-IT:B
• Description: MICMT29F8G08ABABAWP-IT:B 8GB ASYNCHRONOU
• Manufacturer: Micron Technology Inc

Specifications of MT29F8G08ABABAWP-IT:B

• Cell Type: NAND
• Density: 8Gb
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 30b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 1G
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Compliant

Bus Operation
Asynchronous Interface
Table 3:
Asynchronous Enable/Standby
PDF: 09005aef8386131b / Source: 09005aef838cad98
m61a_async_sync_nand.fm - Rev. A 2/09 EN
Mode
Standby
Bus idle
Command input
Address input
Data input
Data output
Write protect
Asynchronous Interface Mode Selection
Notes:
2. WP# should be biased to CMOS LOW or HIGH for standby.
3. Mode selection settings for this table: H = Logic level HIGH; L = Logic level LOW; X = VIH or
These NAND Flash devices have two interfaces: a synchronous interface for fast data I/O
transfer and an asynchronous interface that is backwards compatible with existing
NAND Flash devices.
The NAND Flash command protocol for both the asynchronous and synchronous inter-
faces is identical. However, there are some differences between the asynchronous and
synchronous interfaces when issuing command, address, and data I/O cycles using the
NAND Flash signals.
The asynchronous interface is active when the NAND Flash device powers on to provide
compatibility with existing NAND controllers that may not support the synchronous
interface. The DQS signal is tri-stated when the asynchronous interface is active.
Asynchronous interface bus modes are summarized in Table 3 on page 16.
1. DQS is tri-stated when the asynchronous interface is active.
A target is disabled when CE# is driven HIGH, even when the target is busy. When CE# is
driven LOW, all of the signals for that target are enabled. With CE# LOW, the target can
accept commands, addresses, and data I/O. There may be more than one target in a
NAND Flash package. Each target is controlled by its own CE#; the first target is
controlled by CE#; the second target (if present) is controlled by CE2#, etc.
A target is disabled when CE# is driven HIGH, even when the target is busy. All of the
target's signals are disabled except CE#, WP#, and R/B#. This enables the NAND Flash to
share the same memory bus with other Flash or SRAM devices. While the target is
disabled, other devices on the memory bus can be accessed.
CE#
H
X
L
L
L
L
L
VIL.
CLE
X
X
H
X
L
L
L
Micron Confidential and Proprietary
8Gb Asychronous/Synchronous NAND Flash Memory
ALE
H
X
X
X
L
L
L
16
WE#
X
H
H
X
Micron Technology, Inc., reserves the right to change products or specifications without notice.
RE#
H
H
H
H
X
X
DQS
X
X
X
X
X
X
X
1
©2008 Micron Technology, Inc. All rights reserved.
DQ[7:0]
I/O[7:0]
X
X
X
X
X
X
X
Bus Operation
0V/VccQ
WP#
Advance
X
H
H
H
X
L
2
2