MT29F8G08ABABAWP-IT:B Micron Technology Inc, MT29F8G08ABABAWP-IT:B Datasheet - Page 32

• Manufacturer Part Number: MT29F8G08ABABAWP-IT:B
• Description: MICMT29F8G08ABABAWP-IT:B 8GB ASYNCHRONOU
• Manufacturer: Micron Technology Inc

Specifications of MT29F8G08ABABAWP-IT:B

• Cell Type: NAND
• Density: 8Gb
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 30b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 1G
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Compliant

Synchronous DDR Data Output
PDF: 09005aef8386131b / Source: 09005aef838cad98
m61a_async_sync_nand.fm - Rev. A 2/09 EN
Data can be output from a LUN if it is ready. Data output is supported following a READ
operation from the NAND Flash array.
To enter the DDR data output mode, the following conditions must be met:
• CLK is running,
• CE# is LOW,
• The host has released the DQ[7:0] bus and DQS,
• W/R# is latched LOW on the rising edge of CLK to enable the selected LUN to take
•
• ALE and CLE are HIGH on the rising edge of CLK.
Upon entering the DDR data output mode, DQS will toggle HIGH and LOW with a delay
of
edge-aligned to the rising and falling edges of DQS, with the first transition delayed by
no more than
DDR data output mode continues as long as:
• CLK is running,
• CE# is LOW,
• W/R# is LOW, and
• ALE and CLE are HIGH on the rising edge of CLK.
To exit DDR data output mode, the following conditions must be met:
• CLK is running,
• CE# is LOW,
• W/R# is LOW, and
• ALE and CLE are latched LOW on the rising edge of CLK.
The final two data bytes will be output on DQ[7:0] on the final rising and falling edges of
DQS. The final rising and falling edges of DQS occur
data output sequence where ALE and CLE are latched HIGH. After
enters bus idle mode, and
the host can disable the target if desired.
Data output requests are typically ignored by a LUN that is busy; however, it is possible
to output data from the status register even when a LUN is busy by issuing the READ
STATUS (70h) or SELECT LUN WITH STATUS (78h) command.
t
ownership of the DQ[7:0] bus and DQS within
t
DQSCK from the respective rising and falling edges of CLK. DQ[7:0] will output data
CAD is met, and
Micron Confidential and Proprietary
t
AC.
8Gb Asychronous/Synchronous NAND Flash Memory
t
CAD begins on the next rising edge of CLK. After
32
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
WRCK,
t
DQSCK after the last cycle in the
©2008 Micron Technology, Inc. All rights reserved.
t
CKWR, the bus
Bus Operation
t
CAD starts,
Advance