MT29F8G08ABABAWP-IT:B Micron Technology Inc, MT29F8G08ABABAWP-IT:B Datasheet - Page 59

• Manufacturer Part Number: MT29F8G08ABABAWP-IT:B
• Description: MICMT29F8G08ABABAWP-IT:B 8GB ASYNCHRONOU
• Manufacturer: Micron Technology Inc

Specifications of MT29F8G08ABABAWP-IT:B

• Cell Type: NAND
• Density: 8Gb
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 30b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 1G
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Compliant

Column Address Operations
CHANGE READ COLUMN (05h-E0h)
Figure 38:
SELECT CACHE REGISTER (06h-E0h)
PDF: 09005aef8386131b / Source: 09005aef838cad98
m61a_async_sync_nand.fm - Rev. A 2/09 EN
I/O[7:0] (DQ[7:0])
CHANGE READ COLUMN (05h–E0h) Operation
Cycle type
SR[6]
The column address operations affect how data is input to and output from the cache
registers within the target LUNs. These features provide host flexibility for managing
data, especially when the host internal buffer is smaller than the number of data bytes or
words in the cache register.
When the asynchronous interface is active, column address operations can address any
byte in the selected cache register.
When the synchronous interface is active, column address operations are aligned to
word boundaries (CA0 is forced to "0"), because as data is transferred on DQ[7:0] in two-
byte units.
The CHANGE READ COLUMN (05h-E0h) command changes the column address of the
selected cache register and enables data output from the last selected LUN. This
command is accepted by the selected LUN when it is ready (RDY = 1; ARDY = 1). It is also
accepted by the selected LUN during CACHE READ operations (RDY = 1; ARDY = 0).
Writing 05h to the command register, followed by two column address cycles containing
the column address, followed by the E0h command, puts the selected LUN into data
output mode. After the E0h command cycle is issued, the host must wait at least
before requesting data output. The selected LUN stays in data output mode until
another valid command is issued.
In devices with more than one LUN per target, during and following multi-LUN opera-
tions, the SELECT LUN WITH STATUS (78h) command must be issued prior to issuing
the CHANGE READ COLUMN (05h-E0h). In this situation, using the CHANGE READ
COLUMN (05h-E0h) command without the SELECT LUN STATUS (78h) command will
result in bus contention, as two or more LUNs could output data.
The SELECT CACHE REGISTER (06h-E0h) command enables data output on the
addressed LUN’s cache register at the specified column address. This command is
accepted by a LUN when it is ready (RDY = 1; ARDY = 1).
Writing 06h to the command register, followed by two column address cycles and three
row address cycles, followed by E0h, enables data output mode on the address LUN’s
cache register at the specified column address. After the E0h command cycle is issued,
the host must wait at least
data output mode until another valid command is issued.
D
Dn
OUT
Dn + 1
D
OUT
t RHW
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Command
05h
8Gb Asychronous/Synchronous NAND Flash Memory
Address
t
C1
CCS before requesting data output. The selected LUN stays in
59
Address
C2
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Command
E0h
t CCS
Command Definitions
D
Dk
OUT
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Dk + 1
D
OUT
Dk + 2
D
OUT
Advance
t
CCS