MT29F8G08ABABAWP-IT:B Micron Technology Inc, MT29F8G08ABABAWP-IT:B Datasheet - Page 60

• Manufacturer Part Number: MT29F8G08ABABAWP-IT:B
• Description: MICMT29F8G08ABABAWP-IT:B 8GB ASYNCHRONOU
• Manufacturer: Micron Technology Inc

Specifications of MT29F8G08ABABAWP-IT:B

• Cell Type: NAND
• Density: 8Gb
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 30b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 1G
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Compliant

Figure 39:
CHANGE WRITE COLUMN (85h)
PDF: 09005aef8386131b / Source: 09005aef838cad98
m61a_async_sync_nand.fm - Rev. A 2/09 EN
Cycle
type
I/O[7:0]
(DQ[7:0])
D
Dn
OUT
SELECT CACHE REGISTER (06h–E0h) Operation
Dn + 1
D
OUT
t RHW
Command
Following a multi-plane read page operation, the SELECT CACHE REGISTER (06h-E0h)
command is used to select the cache register to be enabled for data output. After data
output is complete on the selected plane, the command can be issued again to begin
data output on another plane.
In devices with more than one LUN per target, after all of the LUNs on the target are
ready (RDY = 1), the SELECT CACHE REGISTER (06h-E0h) command can be used
following a multi-LUN read operation. LUNs that are not addressed are deselected to
avoid bus contention.
In devices with more than one LUN per target, during multi-LUN operations where
more than one or more LUNs are busy (RDY = 1; ARDY = 0 or RDY = 0; ARDY = 0), the
SELECT LUN WITH STATUS (78h) command must be issued to the target LUN prior to
issuing the SELECT CACHE REGISTER (06h-E0h). In this situation, using the SELECT
CACHE REGISTER (06h-E0h) command without the SELECT LUN STATUS (78h)
command will result in bus contention, as two or more LUNs could output data.
If there is a need to update the column address without selecting a new cache register or
LUN, the CHANGE READ COLUMN (05h-E0h) command can be used instead.
The CHANGE WRITE COLUMN (85h) command changes the column address of the
selected cache register and enables data input on the last-selected LUN. This command
is accepted by the selected LUN when it is ready (RDY = 1; ARDY = 1). It is also accepted
by the selected LUN during cache program operations (RDY = 1; ARDY = 0).
Writing 85h to the command register, followed by two column address cycles containing
the column address, puts the selected LUN into data input mode. After the second
address cycle is issued, the host must wait at least
selected LUN stays in data input mode until another valid command is issued. Though
data input mode is enabled, data input from the host is optional. Data input begins at
the column address specified.
The CHANGE WRITE COLUMN (85h) command is supported prior to the final
command cycle (10h, 11h, 15h) of the following commands:
In devices that have more than one LUN per target, the CHANGE WRITE COLUMN (85h)
command can be used with other commands that support multi-LUN operations.
06h
– PROGRAM PAGE (80h-10h)
– PROGRAM PAGE MULTI-PLANE (80h-11h)
– PROGRAM PAGE CACHE (80h-15h)
– COPYBACK PROGRAM (85h-10h)
– COPYBACK PROGRAM MULTI-PLANE (85h-11h)
Address
C1
Micron Confidential and Proprietary
Address
C2
8Gb Asychronous/Synchronous NAND Flash Memory
Address
R1
60
Address
R2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Address
R3
Command
t
CCS before inputting data. The
E0h
Command Definitions
t CCS
©2008 Micron Technology, Inc. All rights reserved.
D
Dk
OUT
Dk + 1
D
OUT
Advance
Dk + 2
D
OUT