MT29F8G08ABABAWP-IT:B Micron Technology Inc, MT29F8G08ABABAWP-IT:B Datasheet - Page 63

• Manufacturer Part Number: MT29F8G08ABABAWP-IT:B
• Description: MICMT29F8G08ABABAWP-IT:B 8GB ASYNCHRONOU
• Manufacturer: Micron Technology Inc

Specifications of MT29F8G08ABABAWP-IT:B

• Cell Type: NAND
• Density: 8Gb
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 30b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 1G
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Compliant

READ MODE (00h)
PDF: 09005aef8386131b / Source: 09005aef838cad98
m61a_async_sync_nand.fm - Rev. A 2/09 EN
= 1, ARDY = 0). The cache register becomes available and the page requested in the
READ PAGE CACHE operation is transferred to the data register. At this point, data can
be output from the cache register, beginning at column address 0. The CHANGE READ
COLUMN (05h-E0h) command can be used to change the column address of the data
output by the LUN.
After outputting the desired number of bytes from the cache register, either an addi-
tional READ PAGE CACHE-series (31h, 00h-31h) operation can be started or the READ
PAGE CACHE LAST (3Fh) command can be issued.
If an additional READ PAGE CACHE-series (31h, 00h-31h) command is issued, R/B# goes
LOW on the target, RDY = 0 and ARDY = 0 on the LUN for
copied to the cache register, then the next page begins copying into the data register.
After
is available for data output and that the specified page is copying from the NAND Flash
array to the data register. Data can then be output from the cache register, beginning at
column address 0. The CHANGE READ COLUMN (05h-E0h) command can be used to
change the column address of the data being output by the cache register.
If the READ PAGE CACHE LAST (3Fh) command is issued, R/B# goes LOW on the target,
RDY = 0 and ARDY = 0 on the LUN for
cache register. After
cache register is available and that the LUN is ready. Data can then be output from the
cache register, beginning at column address 0. The CHANGE READ COLUMN (05h-E0h)
command can be used to change the column address of the data being output.
For READ PAGE CACHE-series (31h, 00h-31h, 3Fh), during the LUN busy time,
when RDY = 0 and ARDY = 0, the only valid commands are status operations (70h, 78h)
and RESET (FFh, FCh). When RDY = 1 and ARDY = 0, the only valid commands during
READ PAGE CACHE-series (31h, 00h-31h) operations are status operations (70h, 78h),
READ MODE (00h), READ PAGE CACHE-series (31h, 00h-31h), CHANGE READ
COLUMN (05h-E0h), and RESET (FFh, FCh).
PAGE READ MULTI-PLANE Operations Using Cache Operations
PAGE READ MULTI-PLANE Operations Using Cache improve data throughput by
copying data from multiple planes to the specified cache registers simultaneously then
queuing additional planes to be read from the NAND array while the pervious data read
from the NAND array is outputted. This is done by prepending READ PAGE MULTI-
PLANE (00h-32h) commands in front of the PAGE READ CACHE RANDOM (00h-31h)
command.
When the LUN is ready, the SELECT CACHE REGSITER (06h-E0h) command determines
which plane outputs data. During data output the following commands can be used to
read and modify the data in the cache registers: CHANGE READ COLUMN (05h-E0h),
CHANGE ROW ADDRESS (85h).
See “Multi-Plane Operations” on page 86 for additional multi-plane addressing require-
ments.
The READ MODE (00h) command disables status output, and enables data output for
the last-selected LUN and cache register, after a READ operation (00h-30h, 00h-35h) has
been monitored with a STATUS operation (70h, 78h). This command is accepted by the
LUN when it is ready (RDY = 1, ARDY = 1). It is also accepted by the LUN during READ
PAGE CACHE (31h, 3F, 00h-31h) operations (RDY = 1 and ARDY = 0).
t
RCBSY, R/B# goes HIGH, RDY = 1 and ARDY = 0, indicating that the cache register
Micron Confidential and Proprietary
8Gb Asychronous/Synchronous NAND Flash Memory
t
RCBSY, R/B# goes HIGH, RDY = 1 and ARDY = 1, indicating that the
63
t
RCBSY, and the data register is copied into the
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RCBSY, the data register is
Command Definitions
©2008 Micron Technology, Inc. All rights reserved.
t
RCBSY,
Advance