AT45DB642D-CNU SL954 Atmel, AT45DB642D-CNU SL954 Datasheet
AT45DB642D-CNU SL954
Specifications of AT45DB642D-CNU SL954
Related parts for AT45DB642D-CNU SL954
AT45DB642D-CNU SL954 Summary of contents
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... JEDEC Standard Manufacturer and Device ID Read • 100,000 Program/Erase Cycles Per Page Minimum • Data Retention – 20 Years • Green (Pb/Halide-free/RoHS Compliant) Packaging Options • Temperature Range – Industrial: -40°C to +85°C 64-megabit 2.7-volt Dual-interface ® DataFlash AT45DB642D 3542K–DFLASH–04/09 ...
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... To allow for simple in-system reprogrammability, the AT45DB642D does not require high input voltages for programming. The device operates from a single power supply, 2.7V to 3.6V, for both the program and read operations. The AT45DB642D is enabled through the chip select pin (CS) and accessed via a three-wire interface consisting of the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK 8-bit interface consisting of the input/output pins (I/O7 - I/O0) and the clock pin (CLK) ...
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... RDY/BUSY and page-to-buffer transfers. The busy status indicates that the Flash memory array and one of the buffers cannot be accessed; read and write operations to the other buffer can still be performed. 3542K–DFLASH–04/09 ...
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... Figure 2-1. TSOP Top View: Type 1 RDY/BUSY 1 RESET VCC 6 GND SCK/CLK AT45DB642D 4 pin is used to supply the source voltage to the device. CC voltages may produce spurious results and should not be attempted I/O7 25 I/O6 24 I/O5 23 I/O4 22 VCCP 21 GNDP 20 I/O3 19 I/O2 18 I/O1 17 I/O0 16 ...
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... SER/BYTE 4. Memory Array To provide optimal flexibility, the memory array of the AT45DB642D is divided into three levels of granularity comprising of sectors, blocks, and pages. The “Memory Architecture Diagram” illus- trates the breakdown of each level and details the number of pages per sector and block. All program operations to the DataFlash occur on a page by page basis ...
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... The don’t care bytes that follow the address bytes are needed to initialize the read operation. Following the don’t care bytes, additional clock pulses on the SCK/CLK pin will result in data being output on either the SO (serial output) pin or the eight out- put pins (I/O7- I/O0). AT45DB642D 6 Table 15-1 on page 28 through Table 15-6 on 3542K– ...
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... A0). Following the address bytes, additional clock pulses on the SCK pin will result in data being output on the SO (serial output) pin. 3542K–DFLASH–04/09 specification. The Continuous Array Read bypasses both data buf- CAR1 specification ...
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... BFA0). To perform a buffer read from the binary buffer (1024 bytes), the opcode must be clocked into the device followed by three address bytes comprised of 14 don’t care bits and 10 buffer address bits (BFA9 - BFA0). AT45DB642D 8 specification. The Main Memory Page Read bypasses SCK ...
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... Data can be clocked in from the input pins (SI or I/O7 - I/O0) into either buffer 1 or buffer 2. To load data into the standard DataFlash buffer (1056 bytes), a 1-byte opcode, 84H for buffer 1 or 87H for buffer 2, must be clocked into the device, followed by three address bytes comprised of 13 don’ ...
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... PA12/ PA11/ PA10/ PA9/ A22 A21 A20 A19 • • • • • • • • • • • • AT45DB642D 10 PA8/ PA7/ PA6/ PA5/ A18 A17 A16 A15 • • • • • • • • • • • • ...
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... The Sector Erase command can be used to individually erase any sector in the main memory. There are 32 sectors and only one sector can be erased at one time. To perform sector 0a or sector 0b erase for the standard DataFlash page size (1056 bytes), an opcode of 7CH must be loaded into the device, followed by three address bytes comprised of 10 page address bits (PA12 - PA3) and 14 don’ ...
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... Sector Protection Register. The status of whether or not sector protection has been enabled or disabled by either the software or the hardware controlled methods can be deter- mined by checking the Status Register. AT45DB642D 12 Byte 1 Chip Erase ...
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... I/O7-I/O0). After the last bit of the command sequence has been clocked in, the CS pin must be deasserted after which the sector protection will be disabled. The WP pin must be in the deasserted state; otherwise, the Disable Sector Protection command will be ignored. Command Disable Sector Protection Figure 8-2. 3542K–DFLASH–04/09 Byte 1 Enable Sector Protection CS Opcode ...
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... WP Pin and Protection Status Time Period WP Pin Enable Sector Protection Command 1 High 2 Low Command Issued During Period High AT45DB642D 14 time. When the WP pin is deasserted; however, the sector protection WPE 2 Command Not Issued Previously – Issue Command X – Issue Command time) as long as the Enable Sec- ...
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... Sector Protection Register and before 3542K–DFLASH–04/09 Sector Protection Register Sector 0 (0a, 0b) (Page 0-7) Bit 7, 6 (1) 1. The default value for bytes 0 through 31 when shipped from Atmel is 00H don’t care 0 (0a, 0b) See Table 9 ...
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... The Sector Protection Register can be reprogrammed while the sector protection enabled or dis- abled. Being able to reprogram the Sector Protection Register with the sector protection enabled allows the user to temporarily disable the sector protection to an individual sector rather than dis- abling sector protection completely. AT45DB642D 16 Byte 1 3DH ...
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... Command Read Sector Protection Register Note: Figure 9-4. Read Sector Protection Register Opcode Each transition represents 8 bits 3542K–DFLASH–04/09 Opcode Opcode Opcode Byte 2 Byte 3 Byte Dummy Byte Serial Interface = 3 Dummy Bytes Byte 1 Byte 2 Byte 3 3DH 2AH 7FH ...
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... Sector Lockdown com- mand if necessary. Command Sector Lockdown Figure 10-1. Sector Lockdown CS Opcode Byte Each transition represents 8 bits AT45DB642D 18 Byte 1 3DH Opcode Opcode Opcode Address Byte 2 Byte 3 Byte 4 Bytes , during which time the Status P ...
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... Figure 10-2. Read Sector Lockdown Register Opcode Each transition represents 8 bits 3542K–DFLASH–04/09 Sector 0 (0a, 0b) (Page 0-7) Bit 7, 6 details the values read from the Sector Lockdown Register. Sector Lockdown Register xx = Dummy Byte Serial Interface = 3 Dummy Bytes (0a, 0b) See Below ...
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... Therefore not possible to only program the first two bytes of the register and then pro- gram the remaining 62 bytes at a later time. The Program Security Register command utilizes the internal SRAM buffer for processing. Therefore, the contents of the buffer will be altered from its previous state when this command is issued. AT45DB642D 20 Security Register • • • 0 ...
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... Deasserting the CS pin will terminate the Read Security Register operation and put the SO or I/O7 - I/O0 pins into a high-impedance state. Figure 10-4. Read Security Register Opcode Each transition represents 8 bits 3542K–DFLASH–04/09 Opcode Opcode Opcode Data Byte Byte 2 Byte 3 Byte Data Byte Data Byte Data Byte ...
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... The operation is internally self-timed and should take place in a maximum time of t and the RDY/BUSY pin will indicate that the part is busy. AT45DB642D 22 ), the status register can be read or the RDY/BUSY can be XFR ), the status register and the RDY/BUSY pin will indicate that the part is busy ...
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... The device density is indicated using bits and 2 of the status register. For the AT45DB642D, the four bits are 1111 The decimal value of these four binary bits does not equate to the device density; the four bits represent a combinational code relating to differing densities of DataFlash devices ...
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... Deep Power-down, the device will return to the normal standby mode. Command Resume from Deep Power-down Figure 12-2. Resume from Deep Power-Down AT45DB642D 24 time. Once the device has entered the Deep Power-down mode, all EDPD ...
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... Configuration Register is a user-programmable nonvolatile regis- ter that allows the page size of the main memory to be configured for binary page size (1024 bytes) or standard DataFlash page size (1056 bytes). The “power of 2” page size is a one-time programmable configuration register and once the device is configured for “ ...
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... Manufacturer ID codes that are two, three or even four bytes long with the first byte(s) in the sequence being 7FH. A system should detect code 7FH as a “Continuation Code” and continue to read Manufacturer ID bytes. The first non-7FH byte would signify the last byte of Manufacturer ID data. For Atmel (and some other manufacturers), the Manufacturer ID data is comprised of only one byte. AT45DB642D 26 Bit 3 ...
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... Group C can be executed. The Group B commands using buffer 1 should use Group C commands using buffer 2 and vice versa. Finally, during the internally self- timed portion of a Group D command, only the Status Register Read command should be executed. 3542K–DFLASH–04/09 27 ...
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... Buffer 1 to Main Memory Page Program without Built-in Erase Buffer 2 to Main Memory Page Program without Built-in Erase Page Erase Block Erase Sector Erase Chip Erase Main Memory Page Program Through Buffer 1 Main Memory Page Program Through Buffer 2 AT45DB642D 28 Serial/8-bit Opcode Both D2H Both E8H ...
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... Main Memory Page to Buffer 2 Compare Auto Page Rewrite through Buffer 1 Auto Page Rewrite through Buffer 2 Deep Power-down Resume from Deep Power-down Status Register Read Manufacturer and Device ID Read 3542K–DFLASH–04/09 Serial/8-Bit Opcode Both 3DH + 2AH + 7FH + A9H Both 3DH + 2AH + 7FH + 9AH ...
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... B9h ABh D1h D2h D3h D4h D6h D7h E8h Notes Don’t Care A = Address Bit *The number with (*) is for 8-bit interface. AT45DB642D 30 Address Byte Address Byte N/A N/A N/A N/A N/A N ...
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... Table 15-6. Detailed Bit-level Addressing Sequence for Standard DataFlash Page Size (1056 Bytes) Page Size = 1056 bytes Opcode Opcode 03h 0Bh 50h 53h 54h 55h 56h 58h 59h 60h 61h 77h 7Ch 81h 82h 83h 84h 85h 86h 87h 88h 89h ...
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... RDY/BUSY bit of the status register or the RDY/BUSY pin to determine whether the program or erase operation was completed. Fixed tim- ing is not recommended. AT45DB642D 32 . During power-up, the internal Power-on Reset circuitry keeps the device in VCSL ...
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... Voltage Extremes referenced in the "Absolute Maximum Ratings" are intended to accommo- + 0.6V CC date short duration undershoot/overshoot condi- tions and does not imply or guarantee functional device operation at these levels for any extended period of time Ind. AT45DB642D -40°C to 85°C 2.7V to 3.6V 33 ...
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... Output Low Voltage OL V Output High Voltage OH Notes and I during a buffer read maximum. CC1 CC2 2. All inputs (SI, SCK, CS#, WP#, and RESET#) are guaranteed by design to be 5-Volt tolerant. AT45DB642D 34 Condition Min CS, RESET all inputs at IH CMOS levels CS, RESET all inputs at IH CMOS levels MHz ...
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... Block Erase Time (8,192/8,448 bytes Sector Erase Time (262,144/270,336 bytes Chip Erase Time CE t RESET Pulse Width RST t RESET Recovery Time REC Note: 1. Values are based on device characterization, not 100% tested in production. 3542K–DFLASH–04/09 Min Typ Max 6.8 6.8 0.1 0 100 2 ...
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... Block Erase Time (8,192/8,448 bytes Sector Erase Time (262,144/270,336 bytes RESET Pulse Width RST t RESET Recovery Time REC Note: Values are based on device characterization, not 100% tested in production. 19. Input Test Waveforms and Measurement Levels < (10 AT45DB642D 36 Min 9 9 0 DRIVING 1.5V ...
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... Waveform 2 – SPI Mode 3 Compatible (for Frequencies MHz) CS SCK/CLK SO SI Note: To operate the device at 50 MHz in SPI mode, the combined CPU setup time and rise/fall time should be less than 2 ns. 3542K–DFLASH–04/09 DEVICE UNDER TEST period. These timing waveforms are valid over the full frequency range (max ...
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... Waveform 4 – RapidS Mode SCK/CLK HIGH 21.5 Waveform 5 – Rapid8 Mode SCK/CLK HIGH IMPEDANCE I/O7 - I/O0 (OUTPUT) I/O7 - I/O0 (INPUT) 21.6 Waveform 6 – Rapid8 Mode SCK/CLK HIGH Z I/O7 - I/O0 (OUTPUT) I/O7 - I/O0 (INPUT) AT45DB642D MHz) MAX CSS VALID OUT VALID MHz) MAX t t ...
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... SCK, the host controller should wait until the next falling edge of SCK to latch the data in. Similarly, the host controller should clock its data out on the rising edge of SCK in order to give the DataFlash a full clock cycle to latch the incoming data in on the next rising edge of SCK. ...
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... Slave clocks out BYTE a (first output byte). F. Master clocks in BYTE a. G. Master clocks in BYTE h (last output byte). 21.9 Reset Timing CS SCK/CLK RESET SO or I/O7 - I/O0 (OUTPUT I/O7 - I/O0 (INPUT) Note: The CS signal should be in the high state before the RESET signal is deasserted. AT45DB642D 40 Function ...
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... CMD 8 bits 8 bits Page Address (A22 - A10) CMD 8 bits 8 bits (PA12 - PA0) (BA10 - BA0/BFA10 - BFA0) FLASH MEMORY ARRAY WRITE I/O INTERFACE SI 8 bits Byte/Buffer Address (A9 - A0/BFA9 - BFA0) 8 bits Byte/Buffer Address BUFFER 2 TO MAIN MEMORY PAGE PROGRAM BUFFER 2 (1024/1056 BYTES) ...
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... Read Operations The following block diagram and waveforms illustrate the various read sequences available. PAGE (1024/1056 BYTES) MAIN MEMORY PAGE TO BUFFER 1 BUFFER 1 (1024/1056 BYTES) BUFFER 1 AT45DB642D 42 BINARY PAGE SIZE 14 DON'T CARE + BFA9-BFA0 CMD X BFA7-0 X···X, BFA10-8 Starts self-timed erase/program operation ...
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... Main Memory Page Read I/O7 - I/O0 (INPUT I/O7 - I/O0 (OUTPUT) 23.2 Main Memory Page to Buffer Transfer (Data from Flash Page Read into Buffer I/O7 - I/O0 (INPUT I/O7 - I/O0 (OUTPUT) 23.3 Buffer Read Each transition represents 8 bits 3542K–DFLASH–04/09 ADDRESS FOR BINARY PAGE SIZE ...
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... Continuous Array Read (Legacy Opcode E8H SCK OPCODE MSB HIGH-IMPEDANCE SO 24.2 Continuous Array Read (Opcode 0BH SCK OPCODE MSB HIGH-IMPEDANCE SO 24.3 Continuous Array Read (Low Frequency: Opcode 03H SCK MSB HIGH-IMPEDANCE SO AT45DB642D ADDRESS BITS 32 DON'T CARE BITS MSB MSB ADDRESS BITS A23 - MSB MSB ...
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... MSB MSB ADDRESS BITS BINARY PAGE SIZE = 14 DON'T CARE + BFA9-BFA0 STANDARD DATAFLASH PAGE SIZE = 13 DON'T CARE + BFA10-BFA0 MSB MSB ADDRESS BITS BINARY PAGE SIZE = 14 DON'T CARE + BFA9-BFA0 STANDARD DATAFLASH PAGE SIZE = OPCODE 13 DON'T CARE + BFA10-BFA0 MSB DATA BYTE MSB DON'T CARE ...
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... Read Sector Protection Register (Opcode 32H SCK MSB HIGH-IMPEDANCE SO 24.8 Read Sector Lockdown Register (Opcode 35H SCK MSB HIGH-IMPEDANCE SO 24.9 Read Security Register (Opcode 77H SCK MSB HIGH-IMPEDANCE SO AT45DB642D OPCODE DON'T CARE MSB OPCODE DON'T CARE MSB OPCODE DON'T CARE ...
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... Status Register Read (Opcode D7H SCK SI 1 MSB HIGH-IMPEDANCE SO 24.11 Manufacturer and Device Read (Opcode 9FH) CS SCK SI HIGH-IMPEDANCE SO Note: Each transition 3542K–DFLASH–04/ OPCODE STATUS REGISTER DATA MSB OPCODE 9FH 1FH DEVICE ID BYTE 1 shown for SI and SO represents one byte (8 bits) ...
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... ADDR (INPUT) I/O7-I/O0 HIGH IMPEDANCE (OUTPUT) 25.2 Main Memory Page Read (Opcode: D2H) CS CLK t SU I/07-I/O0 (INPUT) I/07-I/O0 (OUTPUT) 25.3 Buffer Read (Opcode: 54H or 56H) CS CLK t SU I/O7-I/O0 (INPUT) I/O7-I/O0 (OUTPUT) AT45DB642D DUMMY BYTES ADDR DATA OUT DATA DATA BINARY & STANDARD ...
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... A page can be written using either a Main Memory Page Program operation or a Buffer Write operation followed by a Buffer to Main Memory Page Program operation. 3. The algorithm above shows the programming of a single page. The algorithm will be repeated sequentially for each page within the entire array. 3542K–DFLASH–04/09 CS CLK 0 ...
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... Other algorithms can be used to rewrite portions of the Flash array. Low-power applications may choose to wait until 10,000 cumulative page erase and program operations have accumulated before rewriting all pages of the sector. See application note AN-4 (“Using Atmel’s Serial DataFlash”) for more details. AT45DB642D 50 START ...
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... Ordering Information 27.1 Ordering Code Detail Atmel Designator Product Family Device Density 64 = 64-megabit Interface 2 = Dual Device Revision 3542K–DFLASH–04/ – Device Grade U = Matte Sn lead finish, industrial temperature range (-40°C to +85°C) Package Option CN = 8-lead CASON T = 28-lead 13.4 mm TSOP Ball BGA ...
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... AT45DB642D-CNU-SL954 (4) AT45DB642D-CNU-SL955 AT45DB642D-TU AT45DB642D-CU Notes: 1. The shipping carrier option is not marked on the devices. 2. Standard parts are shipped with the page size set to 1056 bytes. The user is able to configure these parts to a 1024-byte page size if desired. 3. Parts ordered with suffix SL954 are shipped in bulk with the page size set to 1024 bytes. Parts will have a 954 or SL954 marked on them ...
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... E Notes: 1. This package conforms to JEDEC reference MO-183. 2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion 0.15 mm per side and 0.25 mm per side. 3. Lead coplanarity is 0.10 mm maximum. 2325 Orchard Parkway San Jose, CA 95131 R 3542K–DFLASH–04/09 PIN SEATING PLANE A1 TITLE 28T, 28-lead (8 x 13.4 mm) Plastic Thin Small Outline Package, Type I (TSOP) 0º ...
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... All dimensions and tolerance conform to ASME Y 14.5M, 1994. 2. The surface finish of the package shall be EDM Charmille #24-27. 3. Unless otherwise specified tolerance: Decimal ±0.05, Angular ±2 4. Metal Pad Dimensions. 2325 Orchard Parkway San Jose, CA 95131 R AT45DB642D 54 D Top View Side View Pin1 Pad Corner L1 ...
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... Ball Grid Array Dimensions in Millimeters and (Inches). Controlling dimension: Millimeters. 1.00 (0.039) REF 1.00 (0.0394) BSC NON-ACCUMULATIVE 1.00 (0.0394) BSC NON-ACCUMULATIVE 2325 Orchard Parkway San Jose, CA 95131 R 3542K–DFLASH–04/09 6.10(0.240) 5.90(0.232 8.10(0.319) 7.90(0.311) TOP VIEW 4.0 (0.157 BOTTOM VIEW TITLE 24C1, 24-ball ( Array ...
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... B – November 2005 C – March 2006 D – July 2006 E – August 2006 F – August 2006 G – August 2007 H – April 2008 I – February 2009 J – March 2009 K - April 2009 AT45DB642D 56 History Initial release Changed t from 30 µ µs min. VCSL Changed t from max. PUW Changed t from max ...
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... Use Block Erase (opcode 50H alternative. The Block Erase function is not affected by the Chip Erase issue. 30.1.3 Resolution The Chip Erase feature may be fixed with a new revision of the device. Please contact Atmel for the estimated availability of devices with the fix. 3542K–DFLASH–04/09 57 ...
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... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...