MT47H256M8THN-3:H Micron Technology Inc, MT47H256M8THN-3:H Datasheet
MT47H256M8THN-3:H
Specifications of MT47H256M8THN-3:H
Available stocks
Related parts for MT47H256M8THN-3:H
MT47H256M8THN-3:H Summary of contents
Page 1
... MT47H256M8 – 16 Meg Banks x 2 Ranks For the latest component data sheet, refer to Micron’s Web site: Functionality The 2Gb (TwinDie™) DDR2 SDRAM uses Micron’s 1Gb DDR2 monolithic die and, therefore, has similar func- tionality. This TwinDie data sheet is intended to pro- vide a general description, package dimensions, and the ballout only ...
Page 2
... The three balls with dots designate balls that differ from the monolithic versions. PDF: 09005aef83fa94e3/Source: 09005aef8266ac6e 2Gb_twindie_H.fm - Rev DM, DM/RDQS SSQ V DDQ DQ3 SSQ V REF SS WE# BA1 RFU 2 2Gb: x4, x8 TwinDie DDR2 SDRAM Ball Assignments and Descriptions DQS#/NU V SSQ DDQ DQS V NF, DQ7 SSQ V DQ0 V DDQ DDQ DQ2 V NF, DQ5 SSQ V ...
Page 3
... Input On-die termination: ODT enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DDR2 SDRAM. When enabled in normal operation, ODT is applied only to the following balls: DQ, DQS, DQS#, and DM. The ODT input will be ignored if disabled via the LOAD MODE command. ...
Page 4
... Although each die is tested individually within the dual-die package, some TwinDie test results may vary from a like die tested within a monolithic die package. Each DDR2 SDRAM die uses a double data rate architecture to achieve high-speed oper- ation. The DDR2 architecture is essentially a 4n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O balls ...
Page 5
... CAS# ODT1 WE# Figure 3: Functional Block Diagram (16 Meg Banks x 2 Ranks) CS1# RAS# CKE1 CAS# ODT1 WE# PDF: 09005aef83fa94e3/Source: 09005aef8266ac6e 2Gb_twindie_H.fm - Rev. B 7/10 EN 2Gb: x4, x8 TwinDie DDR2 SDRAM Rank 1 (32 Meg banks) Rank 0 (32 Meg banks) CK CK# A[13:0], BA[2:0] DQS, DQS# DQ[3:0] DM Rank 1 ...
Page 6
... Table 6 on page 7. For designs that are expected to last several years and require the flex- ibility to use several DRAM die shrinks, consider using final target theta values (rather than existing values) to account for increased thermal impedances from the reduction in die size. The DDR2 SDRAM device’ ...
Page 7
... JA (°C/W) Airflow = 2m/s θ JB (°C/W) θ JC (°C/W) Airflow = 1m/s 71.8 54.3 54.1 44.8 0.5 (W) Width (W) Lmm x Wmm FBGA 7 2Gb: x4, x8 TwinDie DDR2 SDRAM Electrical Specifications Max Units 150 °C 85 °C is measured in the center of the package, as STG TN-00-15: “Recommended Soldering Parame- ...
Page 8
... CDD2N I CDD3P CDD3N ); CKE is HIGH, CS CDD4W CKE is HIGH, CS CDD4R ), CKE REFRESH command CDD5 8 2Gb: x4, x8 TwinDie DDR2 SDRAM Electrical Specifications Individual Die Status -25E CDD0 DD0 DD2P CDD1 DD1 DD2P CDD2P DD2P DD2P CDD2Q DD2Q DD2P CDD2N DD2N DD2P Fast PDN exit ...
Page 9
... DD0 DD1 DD2N DD2Q DD3N DD3P(FAST) 2%; I must be derated by 20%; I DD2P be derated by 80% (I will increase by this amount if T DD6 option is still enabled) 9 2Gb: x4, x8 TwinDie DDR2 SDRAM Electrical Specifications Individual Die Status -25E CDD6 DD6 DD6 I = 217 CDD7 DD7 DD2P = V /2 ...
Page 10
... E 10 ±0 0.8 TYP 6.4 CTR 8 ±0.1 characterization sometimes occur. Micron Technology, Inc., reserves the right to change products or specifications without notice. 10 2Gb: x4, x8 TwinDie DDR2 SDRAM Package Dimensions Ball A1 ID 1.2 MAX 0.25 MIN ©2010 Micron Technology, Inc. All rights reserved. ...