MT48H32M16LFBF-75 IT:B Micron Technology Inc, MT48H32M16LFBF-75 IT:B Datasheet

MT48H32M16LFBF-75 IT:B

Manufacturer Part Number
MT48H32M16LFBF-75 IT:B
Description
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet

Specifications of MT48H32M16LFBF-75 IT:B

Organization
32Mx16
Density
512Mb
Address Bus
15b
Access Time (max)
8/5.4ns
Maximum Clock Rate
133MHz
Operating Supply Voltage (typ)
1.8V
Package Type
VFBGA
Operating Temp Range
-40C to 85C
Operating Supply Voltage (max)
1.95V
Operating Supply Voltage (min)
1.7V
Supply Current
90mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / Rohs Status
Compliant
Mobile Low-Power SDR SDRAM
MT48H32M16LF – 8 Meg x 16 x 4 banks
MT48H16M32LF/LG – 4 Meg x 32 x 4 banks
Features
• V
• Fully synchronous; all signals registered on positive
• Internal, pipelined operation; column address can
• Four internal banks for concurrent operation
• Programmable burst lengths: 1, 2, 4, 8, and continu-
• Auto precharge, includes concurrent auto precharge
• Auto refresh and self refresh modes
• LVTTL-compatible inputs and outputs
• On-chip temperature sensor to control self refresh
• Partial-array self refresh (PASR)
• Deep power-down (DPD)
• Selectable output drive strength (DS)
• 64ms refresh period
Table 1: Configuration Addressing
Table 2: Key Timing Parameters
PDF: 09005aef82ea3742
512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN
Architecture
Number of banks
Bank address balls
Row address balls
Column address balls
edge of system clock
be changed every clock cycle
ous
rate
Note:
Note:
DD
Speed Grade
/V
DDQ
-75
1. Contact factory for availability
1. CL = CAS (READ) latency
-6
= 1.7–1.95V
Products and specifications discussed herein are subject to change by Micron without notice.
CL = 2
104
104
Clock Rate (MHz)
32 Meg x 16
BA0, BA1
A[12:0]
A[9:0]
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
4
CL = 3
166
133
1
Notes:
Options
• V
• Addressing
• Configuration
• Plastic “green” packages
• Timing – cycle time
• Power
• Operating temperature range
• Revision
– Standard addressing option
– Reduced page-size option
– 32 Meg x 16 (8 Meg x 16 x 4 banks)
– 16 Meg x 32 (4 Meg x 32 x 4 banks)
– 54-ball VFBGA (8mm x 9mm)
– 90-ball VFBGA (10mm x 13mm)
– 6ns at CL = 3
– 7.5ns at CL = 3
– Standard I
– Low-power I
– Commercial (0˚C to +70˚C)
– Industrial (–40˚C to +85˚C)
DD
Micron Technology, Inc. reserves the right to change products or specifications without notice.
/V
16 Meg x 32
1. Contact factory for availability.
2. Available only for x16 configuration.
3. Available only for x32 configuration.
BA0, BA1
DDQ
A[12:0]
A[8:0]
4
: 1.8V/1.8V
CL = 2
DD2
8ns
8ns
DD2
/I
DD7
/I
DD7
Access Time
1
© 2007 Micron Technology, Inc. All rights reserved.
16 Meg x 32 Reduced
Page-Size Option
1
2
BA0, BA1
A[13:0]
3
A[7:0]
CL = 3
4
5.4ns
5ns
Features
Marking
32M16
16M32
None
None
CM
-75
LG
LF
BF
-6
IT
:B
H
L
1

Related parts for MT48H32M16LFBF-75 IT:B

MT48H32M16LFBF-75 IT:B Summary of contents

Page 1

... CL = CAS (READ) latency Note: PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN Products and specifications discussed herein are subject to change by Micron without notice. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Options • V • Addressing – Standard addressing option – Reduced page-size option • Configuration – ...

Page 2

... FBGA Part Marking Decoder Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. Micron’s FBGA part marking decoder is available at www.micron.com/decoder. PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM 48 H 32M16 LF BF -75 2 Micron Technology, Inc ...

Page 3

... Rev. G, Production – 8/09 ............................................................................................................................ 85 Rev. F, Production – 4/09 ............................................................................................................................ 85 Rev. E, Production – 3/09 ............................................................................................................................ 85 PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM 3 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2007 Micron Technology, Inc. All rights reserved. ...

Page 4

... Update – 7/08 ............................................................................................................................................ 86 Update – 5/08 ............................................................................................................................................ 86 Update – 4/08 ............................................................................................................................................ 86 PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM 4 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2007 Micron Technology, Inc. All rights reserved. ...

Page 5

... Table 18: Truth Table – CKE .......................................................................................................................... 37 Table 19: Burst Definition Table .................................................................................................................... 42 PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM 5 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2007 Micron Technology, Inc. All rights reserved. ...

Page 6

... Figure 47: Auto Refresh Mode ........................................................................................................................ 77 Figure 48: Self Refresh Mode ......................................................................................................................... 79 Figure 49: Power-Down Mode ....................................................................................................................... 80 Figure 50: Clock Suspend During WRITE Burst ............................................................................................... 82 PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM t t RCD (MIN)/ CK < 3 ......................................................... 46 6 Micron Technology, Inc. reserves the right to change products or specifications without notice. ...

Page 7

... Figure 51: Clock Suspend During READ Burst ................................................................................................ 83 Figure 52: Clock Suspend Mode ..................................................................................................................... 84 PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM 7 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2007 Micron Technology, Inc. All rights reserved. ...

Page 8

... General Description The 512Mb Mobile LPSDR is a high-speed CMOS, dynamic random-access memory con- taining 536,870,912-bits internally configured as a quad-bank DRAM with a syn- chronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x16’s 134,217,728-bit banks is organized as 8192 rows by 1K columns by 16 bits. Each of the x32’ ...

Page 9

... CAS# RAS# EXT mode register Refresh counter Mode register Address Address BA0, BA1 register PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Row Bank0 row address address MUX latch and decoder Sense amplifiers I/O gating 2 DQM mask logic ...

Page 10

... DQ14 C DQ12 D DQ10 E DQ8 F UDQM The E2 pin must be connected to V Note: PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Ball Assignments and Descriptions DQ15 V SSQ DQ13 V DDQ DQ11 V SSQ DQ9 V DDQ 1 DNU V SS CLK CKE A11 ...

Page 11

... DQM1 DNU L V DQ8 DDQ M V DQ10 SSQ N V DQ12 SSQ P DQ11 V DDQ R DQ13 DQ15 1. The K2 pin must be connected to V Note: PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM SSQ DQ25 DQ30 A12 DQ9 DQ14 V SSQ V ...

Page 12

... Type Description CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. CKE Input Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the ...

Page 13

... The pre reflow balls are Ø0.42 on Ø0.4 SMD ball pads. 3.2 6.4 0.8 TYP 3 All dimensions are in millimeters. Note: PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM 0.65 ±0.05 8 ±0.1 Ball ±0. 4.5 ±0. ± 0.1 ...

Page 14

... Solder ball material: SAC105. Dimensions apply to solder balls post- reflow on Ø0 SMD ball pads. 11.2 CTR 0.8 TYP 1. 1. All dimensions are in millimeters. Note: PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM 0.65 ±0.1 Ball ±0.1 H ...

Page 15

... IN DD Output leakage current: DQ are disabled; 0V ≤ V Operating temperature: 1. All voltages referenced to V Notes full initialization sequence is required before proper device operation is ensured PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Symbol DDQ ...

Page 16

... Note 1 applies to all parameters and conditions Parameter Input capacitance: CLK Input capacitance: All other input-only balls Input/output capacitance This parameter is sampled. V Note: PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Symbol , V DD DDQ = 1 MHz. 16 Electrical Specifications Min ...

Page 17

... RCD met; No accesses in progress Operating current: Burst mode; READ or WRITE; All banks active, half DQ toggling every cycle Auto refresh current: CKE = HIGH; CS# = HIGH Deep power-down PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Electrical Specifications – I Parameters 1.70–1.95V DD ...

Page 18

... CKE is HIGH during REFRESH command period 8. Typical values at 25˚C (not a maximum value). 9. Enables on-die refresh and address counters. 10. Values for I PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Electrical Specifications – DDQ Full array, 85˚C Full array, 45˚ ...

Page 19

... PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Electrical Specifications – 100 105 Temperature (°C) 19 Micron Technology, Inc. reserves the right to change products or specifications without notice. Parameters ...

Page 20

... AUTO REFRESH period PRECHARGE command period ACTIVE bank a to ACTIVE bank b command Transition time WRITE recovery time Exit SELF REFRESH-to-ACTIVE command PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Electrical Specifications – AC Operating Conditions -6 Symbol Min Max t – ...

Page 21

... The clock frequency must remain constant (stable clock is defined as a signal cycling with This device requires 8192 AUTO REFRESH cycles every 64ms ( 9. AC characteristics assume PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Electrical Specifications – AC Operating Conditions tion over the full temperature range (0˚C ≤ T ≤ T ≤ ...

Page 22

... Timing is specified by 16. Based on PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Electrical Specifications – AC Operating Conditions ns reduction in slew rate. Input hold times remain unchanged. If the slew rate exceeds 4.5V/ns, functionality is uncertain. after the first clock delay and after the last WRITE is executed. ...

Page 23

... Table values based on nominal impedance of 25Ω (full drive strength Notes: 2. The full variation in drive current, from minimum to maximum (due to process, voltage, PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Pull-Down Current (mA) Min Max 0.00 0.00 2 ...

Page 24

... Table values based on nominal impedance of 37Ω (three-quarter drive strength Notes: 2. The full variation in drive current, from minimum to maximum (due to process, voltage, PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Pull-Down Current (mA) Min Max 0.00 0.00 1 ...

Page 25

... Notes: 2. The full variation in drive current, from minimum to maximum (due to process, voltage, 3. The I-V curve for one-quarter drive strength is approximately 50% of one-half drive PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Pull-Down Current (mA) Min Max 0.00 ...

Page 26

... Functional Description Mobile LPSDR devices are quad-bank DRAM that operate at 1.8V and include a synchro- nous interface. All signals are registered on the positive edge of the clock signal, CLK. Read and write accesses to the device are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed se- quence ...

Page 27

... Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” 9. A[11:0] define the op-code written to the mode register. 10. Activates or deactivates the DQ during WRITEs (zero-clock delay) and READs (two-clock PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM CS# RAS# CAS# WE# DQM ...

Page 28

... CLK CKE RAS# CAS# WE# Address BA0, BA1 PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM t MRD is met. HIGH CS# Row address Bank address Don’t Care 28 Micron Technology, Inc. reserves the right to change products or specifications without notice. ...

Page 29

... RAS# CAS# WE# Address A10 BA0, BA1 enable auto precharge, DIS AP = disable auto precharge. Note: PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM HIGH CS# Column address DIS AP Bank address 29 Don’t Care Micron Technology, Inc. reserves the right to change products or specifications without notice. ...

Page 30

... CKE RAS# CAS# WE# Address A10 BA0, BA1 Note enable auto precharge, DIS AP = disable auto precharge. PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM HIGH CS# Column address DIS AP Bank address Valid address 30 Don’t Care Micron Technology, Inc. reserves the right to change products or specifications without notice. ...

Page 31

... BURST TERMINATE command is truncated. AUTO REFRESH AUTO REFRESH is used during normal operation and is analogous to CAS#-BEFORE- RAS# (CBR) REFRESH in FPM/EDO DRAM. Addressing is generated by the internal refresh controller. This makes the address bits “Don’t Care” during an AUTO REFRESH command. PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – ...

Page 32

... SELF REFRESH The SELF REFRESH command is used to place the device in self refresh mode. The self refresh mode is used to retain data in the SDRAM while the rest of the system is pow- ered down. When in self refresh mode, the device retains data without external clock- ing ...

Page 33

... This table is bank-specific, except where noted (for example, the current state is for a 3. Current state definitions: 4. The following states must not be interrupted by a command issued to the same bank. PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM RAS# CAS# WE# Command/Action X X ...

Page 34

... This command is BURST TERMINATE when CKE is HIGH and DEEP POWER-DOWN when PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Read with auto precharge enabled: Starts with registration of a READ command with auto precharge enabled and ends when bank will be in the idle state ...

Page 35

... This table applies when CKE Notes: 2. This table describes alternate bank operation, except where noted; for example, the cur- 3. Current state definitions: PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM RAS# CAS# WE# Command/Action COMMAND INHIBIT (NOP/continue previous operation) ...

Page 36

... For a WRITE with auto precharge interrupted by a WRITE (with or without auto pre- PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Read with auto precharge enabled: Starts with registration of a READ command with auto precharge enabled and ends when bank will be in the idle state ...

Page 37

... Reading or writing H 1. CKE Notes: 2. Current state is the state of the SDRAM immediately prior to clock edge n. 3. COMMAND 4. All states and sequences not shown are illegal or reserved. 5. Exiting power-down at clock edge n will put the device in the all banks idle state in time 6. Exiting self refresh at clock edge n will put the device in the all banks idle state after 7 ...

Page 38

... Initialization Low-power SDRAM devices must be powered up and initialized in a predefined man- ner. Using initialization procedures other than those specified may result in undefined operation. After power is simultaneously applied to V ble (a stable clock is defined as a signal cycling within timing constraints specified for the clock ball), the device requires a 100μs delay prior to issuing any command other than a COMMAND INHIBIT or NOP. Starting at some point during this 100μ ...

Page 39

... T = 100µs Power-up: V and DD CLK stable 1. PRE = PRECHARGE command AUTO REFRESH command, LMR = LOAD MODE REGIS- Notes: 2. NOPs or DESELECTs must only be provided during 3. NOPs or DESELECTs must only be provided during PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM ...

Page 40

... Extended mode register 1 1 Reserved Write Burst Mode M9 Programmed burst length 0 Single location access – PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM t MRD before initiating the subsequent operation. Violating either of these require- ... A10 ... M10 ...

Page 41

... The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address. PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM 41 Micron Technology, Inc. reserves the right to change products or specifications without notice. Mode Register ...

Page 42

... Starting Column Address Continuous n = A0–An/9/8 (location 0–y) PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Order of Accesses Within a Burst Type = Sequential A0 0 0 0-1-2-3 1 1-2-3-0 0 2-3-0-1 1 3-0-1 0-1-2-3-4-5-6-7 1 1-2-3-4-5-6-7-0 0 2-3-4-5-6-7-0-1 1 3-4-5-6-7-0-1-2 0 4-5-6-7-0-1-2-3 1 5-6-7-0-1-2-3-4 0 6-7-0-1-2-3-4-5 ...

Page 43

... When the burst length programmed via M[2:0] applies to both READ and WRITE bursts; when the programmed burst length applies to READ bursts, but write accesses are single-location (nonburst) accesses. PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM T0 T1 CLK READ ...

Page 44

... Programming the temperature-compensated self refresh (TCSR) bits has no effect on the device. The self refresh oscillator will continue refresh at the optimal factory-programmed rate for the device temperature. PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM BA0 An ... A10 ...

Page 45

... These are full, three-quarter, one-half, and one-quarter drive strengths, respectively. PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM 45 Micron Technology, Inc. reserves the right to change products or specifications without notice. Extended Mode Register © 2007 Micron Technology, Inc. All rights reserved. ...

Page 46

... Bank/Row Activation Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be opened. This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated. After a row is opened with the ACTIVE command, a READ or WRITE command can be ...

Page 47

... READ command. Full-speed random read accesses can be per- formed to the same bank, or each subsequent READ can be performed to a different bank. PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM 47 Micron Technology, Inc. reserves the right to change products or specifications without notice. READ Operation ...

Page 48

... Figure 17: Consecutive READ Bursts Command Address Command Address 1. Each READ command can be issued to any bank. DQM is LOW. Note: PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM CLK READ NOP NOP Bank, Col OUT CLK READ NOP ...

Page 49

... If not, the second WRITE will be an invalid WRITE. For example, if DQM was LOW during T4, then the WRITEs at T5 and T7 would be valid, and the WRITE at T6 would be invalid. PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM CLK ...

Page 50

... PRECHARGE command is that it can be used to truncate fixed-length or continuous page bursts. Figure 19: READ-to-WRITE CLK DQM Command Address The READ command can be issued to any bank, and the WRITE command can be Note: PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM READ NOP NOP Bank, Col n DQ Transitioning data to any bank ...

Page 51

... The READ command can be issued to any bank, and the WRITE command can be Note: Figure 21: READ-to-PRECHARGE Command Address Command Address 1. DQM is LOW. Note: PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM CLK READ NOP NOP Bank, Col n DQ Transitioning data to any bank ...

Page 52

... Figure 22: Terminating a READ Burst Command Address Command Address 1. DQM is LOW. Note: PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM CLK READ NOP NOP Bank, Col n ...

Page 53

... Enable auto precharge Row A10 BA0, BA1 Bank RCD - bank 0 t RAS - bank bank 0 t RRD 1. For this example and Note: PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM READ NOP ACTIVE t CMH Row Column m Row Bank 0 Bank ...

Page 54

... Address Row Column A10 Row BA0, BA1 Bank Bank DQ t RCD 1. For this example Note: PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM READ NOP NOP NOP t CMH OUT t LZ All locations within same row CAS latency Full-page burst does not self-terminate ...

Page 55

... AH Row Address Enable auto precharge A10 Row Disable auto precharge BA0, BA1 Bank DQ t RCD 1. For this example and Note: PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM READ NOP NOP t CMH Column m Bank OUT ...

Page 56

... Figure 28 (page 58), or each subsequent WRITE can be performed to a different bank. Figure 26: WRITE Burst Command Address DQM is LOW. Note: PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM CLK WRITE NOP NOP Bank, ...

Page 57

... PRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the command. The advantage of the PRECHARGE command is that it can be used to truncate fixed-length bursts or continu- ous page bursts. PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM CLK WRITE ...

Page 58

... Each WRITE command can be issued to any bank. DQM is LOW. Figure 29: WRITE-to-READ Command Address 1. The WRITE command can be issued to any bank, and the READ command can be to any Note: PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM CLK WRITE WRITE WRITE ...

Page 59

... BURST TERMINATE com- mand. This is shown in Figure 31 (page 60), where data n is the last desired data element of a longer burst. PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM CLK ...

Page 60

... Figure 31: Terminating a WRITE Burst Command Address 1. DQM is LOW. Note: PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM CLK BURST NEXT WRITE TERMINATE COMMAND Bank, Address Col Data IN Transitioning data Don’t Care 60 WRITE Operation Micron Technology, Inc. reserves the right to change products or specifications without notice. ...

Page 61

... Enable auto precharge Row A10 BA0, BA1 Bank 0 Bank RCD - bank 0 t RAS - bank bank 0 t RRD 1. For this example Note: PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM WRITE NOP ACTIVE t CMH Row Row Bank ...

Page 62

... Command ACTIVE NOP DQM Address Row Row A10 BA0, BA1 Bank DQ t RCD 1. Notes: 2. Page left open; no PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM WRITE NOP NOP t CMH t CMS Column m Bank must be satisfied prior to issuing a PRECHARGE command. ...

Page 63

... READ commands access columns according to the programmed burst length and se- quence, just as in the normal mode of operation (M9 = 0). PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM ...

Page 64

... This device supports a single WRITE with auto precharge, issued at be delayed until Micron SDRAM supports concurrent auto precharge; cases of concurrent auto pre- charge for READs and WRITEs are defined below. READ with auto precharge interrupted by a READ (with or without auto precharge) A READ to bank m will interrupt a READ on bank n following the programmed CAS la- tency ...

Page 65

... Figure 35: READ With Auto Precharge Interrupted by a READ CLK Command Bank n Internal states Bank m Address DQ 1. DQM is LOW. Note: PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM met, where READ - AP READ - AP NOP NOP Bank n Bank m Page active ...

Page 66

... Command Page Bank n active Internal States Bank m Address 1 DQM DQ Note: 1. DQM is HIGH prevent D PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM READ - AP NOP NOP NOP Bank n READ with burst of 4 Page active Bank n, Col a D OUT ...

Page 67

... DQM Row Address Enable auto precharge Row A10 BA0, BA1 Bank DQ t RCD t RAS For this example and Note: PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM READ NOP NOP t CMH Column m Bank OUT PRECHARGE Operation ...

Page 68

... Disable auto precharge BA0, BA1 Bank DQ t RCD t RAS For this example and the READ burst is followed by a manual PRECHARGE. Note: PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM READ NOP NOP t CMS t CMH Column m Bank ...

Page 69

... AH Address Row A10 Row BA0, BA1 Bank DQ t RCD t RAS For this example and Note: PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM READ NOP NOP t CMS t CMH Column m Enable auto precharge Bank PRECHARGE Operation ...

Page 70

... AH Disable auto precharge BA0, BA1 Bank DQ t RCD t RAS For this example and the READ burst is followed by a manual PRECHARGE. Note: PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM READ NOP NOP t CMS t CMH Column m ...

Page 71

... Figure 42: WRITE With Auto Precharge Interrupted by a WRITE CLK Command Bank n Internal States Bank m Address DQ 1. DQM is LOW. Note: PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM WRITE - AP READ - AP NOP NOP Bank n Bank m Interrupt burst, write-back Page active ...

Page 72

... NOP t CMS DQM Address Row Column Enable auto precharge A10 Row BA0, BA1 Bank RCD t RAS For this example Note: PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM WRITE NOP NOP t CMH Bank PRECHARGE Operation T5 T6 ...

Page 73

... Row A10 Disable auto precharge BA0, BA1 Bank RCD t RAS For this example and the WRITE burst is followed by a manual PRECHARGE. Note: PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM WRITE NOP NOP NOP t CMH Bank ...

Page 74

... DQM Address Row Enable auto precharge A10 Row BA0, BA1 Bank DQ t RCD t RAS For this example Note: PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM WRITE NOP NOP t CMS t CMH Column m Bank PRECHARGE Operation T5 T6 ...

Page 75

... Disable auto precharge BA0, BA1 Bank DQ t RCD t RAS For this example and the WRITE burst is followed by a manual PRECHARGE. Note: PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM WRITE NOP NOP t CMS t CMH Column m Bank ...

Page 76

... REFRESH command. After the AUTO REFRESH command is initiated, it must not be interrupted by any exe- cutable command until NOP commands must be issued on each positive edge of the clock. The SDRAM re- quires that every row be refreshed each REFRESH command—calculated by dividing the refresh period ( rows to be refreshed—meets the timing requirement and ensures that each row is re- freshed ...

Page 77

... CMH Command PRECHARGE DQM Address All banks A10 Single bank BA0, BA1 Bank(s) High Precharge all active banks 1. Back-to-back AUTO REFRESH commands are not required. Note: PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM AUTO NOP ...

Page 78

... Upon exiting the self refresh mode, AUTO REFRESH commands must be issued accord- ing to the distributed refresh rate ( AUTO REFRESH utilize the row refresh counter. PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM t RAS and remains in self refresh mode for t REF/refresh row count) as both SELF REFRESH and 78 Micron Technology, Inc ...

Page 79

... Address All banks A10 Single bank BA0, BA1 Bank(s) High Precharge all active banks 1. Each AUTO REFRESH command performs a REFRESH cycle. Back-to-back commands are Note: PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM CKS ( ( ) ) ( ...

Page 80

... Precharge all All banks idle, enter active banks power-down mode 1. Violating refresh requirements during power-down may result in a loss of data. Note: PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM CKS NOP NOP Input buffers gated off ...

Page 81

... To exit deep power-down mode, CKE must be asserted HIGH. Upon exiting deep power- down mode, a full initialization sequence is required. PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM 81 Micron Technology, Inc. reserves the right to change products or specifications without notice. Deep Power-Down ...

Page 82

... Figure 50: Clock Suspend During WRITE Burst CLK CKE Internal clock Command Address D Note: 1. For this example greater, and DQM is LOW. PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM NOP WRITE Bank, Col Clock Suspend ...

Page 83

... Figure 51: Clock Suspend During READ Burst CLK CKE Internal clock Command Address DQ 1. For this example greater, and DQM is LOW. Note: PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM READ NOP NOP Bank, Col n D OUT ...

Page 84

... READ NOP t CMS t CMH DQM Address Column A10 BA0, BA1 Bank DQ 1. For this example and auto precharge is disabled. Note: PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM CKH NOP NOP OUT Clock Suspend NOP NOP ...

Page 85

... Strength) tables: Added drive-strength tables. Rev. A, Advance – 10/07 • Initial release. PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM t RFC from 97.5ns to 72ns in Table 10 (page 20). Curves figure: Changed current units on y-axis from mA to µA. DD7 ...

Page 86

... Although considered final, these specifications are subject to change, as further product development and data characterization some- PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM times occur. 86 Micron Technology, Inc. reserves the right to change products or specifications without notice. ...

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