HYB39S256800CTL-8 Infineon Technologies, HYB39S256800CTL-8 Datasheet - Page 12

• Manufacturer Part Number: HYB39S256800CTL-8
• Manufacturer: Infineon Technologies

Specifications of HYB39S256800CTL-8

• Lead Free Status / Rohs Status: Not Compliant

continues until it is terminated using other commands. Full page operation is an optional feature on
this device, which is built in by design, but not tested on every component.
address are possible once the RAS cycle latches the sense amplifiers. The maximum t
refresh interval time limits the number of random column accesses. A new burst access can be
done even before the previous burst ends. The interrupt operation at every clock cycle is supported.
When the previous burst is interrupted, the remaining addresses are overridden by the new address
with the full burst length. An interrupt which accompanies an operation change from a read to a write
is possible by exploiting DQM to avoid bus contention.
are possible. With the programmed burst length, alternate access and precharge operations on two
or more banks can realize fast serial data access modes among many different pages. Once two or
more banks are activated, column to column interleave operation can be performed between
different pages.
Burst Length and Sequence
Refresh Mode
CAS -before-RAS refresh of conventional DRAMs. All banks must be precharged before applying
any refresh mode. An on-chip address counter increments the word and the bank addresses and no
bank information is required for both refresh modes.
are held high at a clock timing. The mode restores word line after the refresh and no external
precharge command is necessary. A minimum tRC time is required between two automatic
INFINEON Technologies
Full Page
(optional)
Similar to the page mode of conventional DRAM’s, burst read or write accesses on any column
When two or more banks are activated sequentially, interleaved bank read or write operations
Length
SDRAM has two refresh modes, Auto Refresh and Self Refresh. Auto Refresh is similar to the
Burst
The chip enters the Auto Refresh mode, when RAS and CAS are held low and CKE and WE
2
4
8
Starting Address
(A2 A1 A0)
000
001
010
011
100
101
110
111
nnn
xx0
xx1
x00
x01
x10
x11
:
Sequential Burst Addressing
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
0
Cn, Cn+1, Cn+2
2
3
4
5
6
7
0
1
(decimal)
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
0, 1
1, 0
3
4
5
6
7
0
1
2
4
5
6
7
0
1
2
3
12
5
6
7
0
1
2
3
4
6
7
0
1
2
3
4
5
7
0
1
2
3
4
5
6
HYB39S256400/800/160CT(L)
256MBit Synchronous DRAM
Interleave Burst Addressing
0
1
2
3
4
5
6
7
1
0
3
2
5
4
7
6
(decimal)
not supported
2
3
0
1
6
7
4
5
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
3
2
1
0
7
6
5
4
0, 1
1, 0
4
5
6
7
0
1
2
3
5
4
7
6
1
0
3
2
6
7
4
5
2
3
0
1
RAS
7
6
5
4
3
2
1
0
or the
8.00