HYB39S256800CTL-8 Infineon Technologies, HYB39S256800CTL-8 Datasheet - Page 9

• Manufacturer Part Number: HYB39S256800CTL-8
• Manufacturer: Infineon Technologies

Specifications of HYB39S256800CTL-8

• Lead Free Status / Rohs Status: Not Compliant

Operation Definition
All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at
the positive edge of the clock. The following list shows the truth table for the operation commands.
Operation
Bank Active
Bank Precharge
Precharge All
Write
Write with Autoprecharge
Read
Read with Autoprecharge
Mode Register Set
No Operation
Burst Stop
Device Deselect
Auto Refresh
Self Refresh Entry
Self Refresh Exit
Clock Suspend Entry
Power Down Entry
(Precharge or active
standby)
Clock Suspend Exit
Power Down Exit
Data Write/Output Enable
Data Write/Output Disable Active
Notes
1. V = Valid, x = Don’t Care, L = Low Level, H = High Level
2. CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock
3. This is the state of the banks designated by BA0, BA1 signals.
4. Power Down Mode can’t be entered in a burst cycle. When this command assert in the burst
INFINEON Technologies
before the commands are provided.
mode cycle device is clock suspend mode.
Device
State
Idle
Any
Any
Active
Active
Active
Active
Idle
Any
Active
Any
Idle
Idle
Idle
(Self
Refr.)
Active
Idle
Active
Active
Any
(Power
Down)
Active
3
3
3
3
3
4
CKE
n-1
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
CKE
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
X
X
n
L
L
L
DQM
9
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
X
X
X
L
BA0
BA1
V
V
X
V
V
V
V
V
X
X
X
X
X
X
X
X
X
X
X
X
HYB39S256400/800/160CT(L)
256MBit Synchronous DRAM
AP=
A10
V
H
H
H
V
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
Addr
V
X
X
V
V
V
V
V
X
X
X
X
X
X
X
X
X
X
X
X
.
CS
H
H
X
H
X
H
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
RAS
H
H
H
H
H
H
H
H
H
L
L
L
L
X
X
X
X
X
X
X
X
L
L
CAS
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
WE
8.00
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L