CY7C4221-15AC

... Features • High-speed, low-power, First-In, First-Out (FIFO) memories — 64 × 9 (CY7C4421) — 256 × 9 (CY7C4201) — 512 × 9 (CY7C4211) — 1K × 9 (CY7C4221) — 2K × 9 (CY7C4231) — 4K × 9 (CY7C4241) — 8K × 9 (CY7C4251) • High-speed 100-MHz operation (10 ns Read/Write cycle time) • Low power (I ...

... CY7C4211 CY7C4221 512 × × 9 Description Data Inputs for 9-bit Bus The only Write enable to have programmable flags when device is configured. Data is written on a LOW-to-HIGH transition of WCLK when WEN1 is asserted and FF is HIGH. If the FIFO is configured to have two Write enables, data is written on a LOW-to-HIGH transition of WCLK when WEN1 is LOW and WEN2/LD and FF are HIGH ...

Functional Description The CY7C42X1 provides four status pins: Empty, Full, Almost Empty, Almost Full. The Almost Empty/Almost Full flags are programmable to single word granularity. The programmable flags default to Empty – 7 and Full – 7. The flags are ...

Empty Offset (LSB) Reg. Default Value = 007h Full Offset (LSB) Reg Default Value = 007h × ...

... Empty Offset ( default value Full Offset ( default value). Document #: 38-06016 Rev. *C CY7C4421/4201/4211/4221 (256 – m), CY7C4211 (512 – m), CY7C4221 (1K – m), CY7C4231 (2K – m), CY7C4241 (4K – m), and CY7C4251 (8K – m). PAF is set HIGH by the LOW-to-HIGH transition of WCLK when the number of available memory locations is greater than m. ...

Width Expansion Configuration Word width may be increased simply by connecting the corre- sponding input controls signals of multiple devices. A composite flag should be created for each of the end-point status flags (EF and FF). The partial status flags ...

Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature ...................................–65 Ambient Temperature with Power Applied...............................................–55 Supply Voltage to Ground Potential ............... –0.5V to +7.0V DC Voltage Applied to Outputs in ...

AC Test Loads and Waveforms R1 1.1 K Ω 5V OUTPUT C L INCLUDING JIG AND Equivalent to: SCOPE Switching Characteristics Over the Operating Range Parameter Description t Clock Cycle Frequency S t Data Access Time A t Clock Cycle ...

Switching Waveforms Write Cycle Timing t CLKH WCLK D – WEN1 WEN2 (if applicable) FF [15] t SKEW1 RCLK REN1,REN2 Read Cycle Timing t CLKH RCLK t t ENS ENH REN1,REN2 EF Q – OLZ ...

Switching Waveforms (continued) [17] Reset Timing RS REN1, REN2 WEN1 [18] WEN2/LD EF,PAE FF,PAF First Data Word Latency after Reset with Simultaneous Read and Write WCLK – (FIRST ...

Switching Waveforms (continued) Empty Flag Timing WCLK t DS DATAWRITE1 D – ENH ENS WEN1 WEN2 (if applicable ENS ENH [20] t FRL RCLK t SKEW1 EF REN1, REN2 LOW OE DATA IN OUTPUT ...

Switching Waveforms (continued) Full Flag Timing NO Write WCLK [15] t SKEW1 D – WFF FF WEN1 WEN2 (if applicable) RCLK t ENH t ENS REN1, REN2 LOW –Q DATA IN OUTPUT REGISTER ...

... If a Write is performed on this rising edge of the Write clock, there will be Full – (m – 1) words of the FIFO when PAF goes LOW. 26. PAF offset = m. 27. 64-m words for CY7C4421, 256 – m words in FIFO for CY7C4201, 512 – m words for CY7C4211, 1024 – m words for CY7C4221, 2048 – m words for CY7C4231, 4096 – m words for CY7C4241, 8192 – m words for CY7C4251. ...

Switching Waveforms (continued) Read Programmable Registers t CLK t CLKH RCLK t ENS WEN2/LD t ENS REN1, REN2 Q – Document #: 38-06016 Rev. *C CY7C4421/4201/4211/4221 t CLKL t ENH t A UNKNOWN PAE OFFSET LSB PAE OFFSET ...

Typical AC and DC Characteristics NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.4 1 25°C 0 100 MHz 0.6 4 4.5 5 5.5 6 SUPPLY VOLTAGE (V) NORMALIZED t vs. SUPPLY ...

... CY7C4211-10JI 15 CY7C4211-15AC CY7C4211-15AXC CY7C4211-15JC CY7C4211-15JXC CY7C4211-15AI 25 CY7C4211-25AC CY7C4211-25JC Synchronous FIFO Speed (ns) Ordering Code 10 CY7C4221-10AC CY7C4221-10JC 15 CY7C4221-15AC CY7C4221-15AXC CY7C4221-15JC CY7C4221-15JXC 25 CY7C4221-25AC CY7C4221-25JC Document #: 38-06016 Rev. *C CY7C4421/4201/4211/4221 Package Package Name Type A32 32-lead Thin Quad Flatpack J65 32-lead Plastic Leaded Chip Carrier J65 ...

Synchronous FIFO Speed (ns) Ordering Code 10 CY7C4231-10AC CY7C4231-10JC 15 CY7C4231-15AC CY7C4231-15AXC CY7C4231-15JC CY7C4231-15JXC 25 CY7C4231-25AC CY7C4231-25JC Synchronous FIFO Speed (ns) Ordering Code 10 CY7C4241-10AC CY7C4241-10AXC CY7C4241-10JC CY7C4241-10JI 15 CY7C4241-15AC CY7C4241-15AXC CY7C4241-15JC CY7C4241-15JXC 25 ...

... Document #: 38-06016 Rev. *C © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress ...

... Change Input Leakage current I RBI Power up requirements added to Maximum Ratings Information ESH Added Pb-Free logo to top of front page Added CY7C4421-10JXC, CY7C4201-15AXC. CY7C4201-15JXC, CY7C4211-10AXI, CY7C4211-15AXC, CY7C4211-15JXC, CY7C4221-15AXC, CY7C4221-15JXC, CY7C4231-15JXC, CY7C4231-15AXC, CY7C4241-10AXC, CY7C4241-15AXC, CY7C4241-15JXC, CY7C4251-10JXC, CY7C4251-10AXI, CY7C4251-15AXC, CY7C4251-15JXC CY7C4421/4201/4211/4221 CY7C4231/4241/4251 unit from mA to µA (typo) ...