IS43DR16320B-37CBL ISSI, Integrated Silicon Solution Inc, IS43DR16320B-37CBL Datasheet - Page 25

• Manufacturer Part Number: IS43DR16320B-37CBL
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: DDR2 SDRAMr

Specifications of IS43DR16320B-37CBL

• Organization: 32Mx16
• Density: 512Mb
• Address Bus: 15b
• Access Time (max): 500ps
• Maximum Clock Rate: 533MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 250mA
• Pin Count: 84
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

IS43/46DR86400B, IS43/46DR16320B
14. User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard active power-down mode” (MRS,
15. Timings are guaranteed with command / address input slew rate of 1.0 V/ns.
16. Timings are guaranteed with data / mask input slew rate of 1.0 V/ns.
17. Timings are guaranteed with CK/CK# differential slew rate 2.0 V/ns, and DQS/DQS# (and RDQS/RDQS#) differential slew rate 2.0 V/ns in differential strobe
18. If refresh timing or tDS/tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed.
19. In all circumstances, tXSNR can be satisfied using tXSNR = tRFC + 10 ns.
20. The tRCD timing parameter is valid for both activate command to read or write command with and without Auto-Precharge. Therefore a separate parameter
21.
22. Definitions:
23. Applicable to certain temperature grades. Specified OPER (Tc and Ta) must not be violated for each temperature grade.
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. E, 01/17/2011
A12 = “0”) a fast power-down exit timing tXARD can be used. In “low active power-down mode” (MRS, A12 =”1”) a slow power-down exit timing tXARDS has to
be satisfied.
mode.
tRAP for activate command to read or write command with Auto-Precharge is not necessary anymore.
tRAS(max) is calculated from the maximum amount of time a DDR2 device can operate without a Refresh command which is equal to 9 x tREFI.
a.
b.
c.
d.
e.
f.
g.
tCK(avg): tCK(avg) is calculated as the average clock period across any consecutive 200 cycle window.
tCH(avg): tCH(avg) is defined as the average HIGH pulse width, as calculated across any consecutive 200 HIGH pulses.
tCL(avg): tCL(avg) is defined as the average LOW pulse width, as calculated across any consecutive 200 LOW pulses.
tJITDTY: tJITDTY is defined as the cumulative set of tCH jitter and tCL jitter. tCH jitter is the largest deviation of any single tCH from tCH(avg). tCL jitter
is the largest deviation of any single tCL from tCL(avg)
tJITPER: tJITPER is defined as the largest deviation of any single tCK from tCK(avg).
tJITCC: tJITCC is defined as the difference in clock period between two consecutive clock cycles: tJITCC is not guaranteed through final production
testing
tERR: tERR is defined as the cumulative error across multiple consecutive cycles from tCK (avg).
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