ISPLSI 1048E-70LQ Lattice, ISPLSI 1048E-70LQ Datasheet
ISPLSI 1048E-70LQ
Specifications of ISPLSI 1048E-70LQ
Related parts for ISPLSI 1048E-70LQ
ISPLSI 1048E-70LQ Summary of contents
Page 1
... The basic unit of logic on the ispLSI 1048E device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1…F7 (see Figure 1). There are a total of 48 GLBs in the ispLSI 1048E device ...
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... GLBs. Delays through the GRP have been equalized to minimize timing skew. Clocks in the ispLSI 1048E device are selected using the Clock Distribution Network. Four dedicated clock pins (Y0, Y1, Y2 and Y3) are brought into the distribution network, and five clock outputs (CLK 0, CLK 1, CLK 2, IOCLK 0 and IOCLK 1) are provided to route clocks to the GLBs and I/O cells ...
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... Input High Voltage IH o Capacitance (T =25 C, f=1.0 MHz) A SYMBOL PARAMETER C Dedicated Input, I/O, Y1, Y2, Y3, Clock Capacitance Clock Capacitance 2 Data Retention Specifications PARAMETER Data Retention Erase/Reprogram Cycles Specifications ispLSI 1048E 1 +1.0V CC +1.0V CC PARAMETER Commercial T = 0° 70°C A Industrial T = -40° 85°C A TYPICAL 15 MINIMUM 20 ...
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... Refer to the Power Consumption CC section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum Specifications ispLSI 1048E Figure 2. Test Load GND to 3.0V ≤ 10% to 90% 1.5V 1.5V ...
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... Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock. 2. Refer to Timing Model in this data sheet for further details. 3. Standard 16-bit counter using GRP feedback. 4. Reference Switching Test Conditions section. Specifications ispLSI 1048E Over Recommended Operating Conditions 1 DESCRIPTION ...
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... Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock. 2. Refer to Timing Model in this data sheet for further details. 3. Standard 16-bit counter using GRP feedback. 4. Reference Switching Test Conditions section. Specifications ispLSI 1048E Over Recommended Operating Conditions 1 DESCRIPTION ...
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... ORP Bypass Delay orpbp 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros. Specifications ispLSI 1048E 1 DESCRIPTION 3 7 -125 -100 -90 MIN ...
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... ORP Bypass Delay orpbp 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros. Specifications ispLSI 1048E 1 DESCRIPTION 3 8 -70 -50 UNITS MIN ...
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... Clock Delay, Clock GLB to I/O Cell Global Clock Line iocp Global Reset t 59 Global Reset to GLB and I/O Registers gr 1. Internal timing parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. Specifications ispLSI 1048E 1 DESCRIPTION 9 -125 -100 -90 MIN. MAX. ...
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... Clock Delay, Clock GLB to I/O Cell Global Clock Line Global Reset t 59 Global Reset to GLB and I/O Registers gr 1. Internal timing parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. Specifications ispLSI 1048E 1 DESCRIPTION 10 -70 -50 UNITS MIN ...
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... Clock (max) + Reg co + Output gy0(max) + gco + = (#54 + #42 + #56) + (#42) + (#47 + #49) 9 (0.9 + 2.3 + 1.8) + (2.3) + (1.0 + 1.3) 1. Calculations are based upon timing specifications for the ispLSI 1048E-125. Specifications ispLSI 1048E GRP GLB Feedback #34 Comb 4 PT Bypass GRP4 Reg 4 PT Bypass GLB Reg Bypass #30 #35 ...
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... Notes: Configuration of twelve 16-bit counters can be estimated for the ispLSI 1048E using the following equation PTs * 0.42 nets * Max. freq * 0.010) Where PTs = Number of Product Terms used in design # of nets = Number of Signals used in device Max. freq = Highest Clock Frequency to the device The I CC estimate is based on typical conditions ( ...
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... SCLK/ RESET 17, 33, GND 97, 112 VCC 16, 48, 82, 1. Pins have dual function capability. Specifications ispLSI 1048E 24, 25, 26, Input/Output Pins - These are the general purpose I/O pins used by the 30, 31, 32, logic array. 37, 38, 39, 44, 43, 45, 55, 56, 57, 61, 62, 63, 69, 70, 71, 76, 75, ...
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... Pin Configuration ispLSI 1048E 128-Pin PQFP Pinout Diagram GND VCC 16 GND 17 ispEN 18 RESET 19 1 SDI Pins have dual function capability. Specifications ispLSI 1048E ispLSI 1048E Top View 14 96 I/O 59 ...
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... Pin Configuration ispLSI 1048E 128-Pin TQFP Pinout Diagram GND VCC 16 GND 17 ispEN 18 RESET 19 1 SDI Pins have dual function capability. Specifications ispLSI 1048E ispLSI 1048E Top View 15 96 I/O 59 ...
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... INDUSTRIAL ORDERING NUMBER 15 ispLSI 1048E-70LQI* 20 ispLSI 1048E-50LQI specification Grade Blank = Commercial I = Industrial Package Q = PQFP T = TQFP QN = Lead-Free PQFP TN = Lead-Free TQFP Power L = Low PACKAGE ...
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... INDUSTRIAL ORDERING NUMBER 15 ispLSI 1048E-70LQNI Previous Lattice release. Updated for lead-free package options. 17 PACKAGE Lead-Free 128-Pin PQFP Lead-Free 128-Pin TQFP Lead-Free 128-Pin PQFP Lead-Free 128-Pin TQFP Lead-Free 128-Pin PQFP Lead-Free 128-Pin TQFP ...