C8051F336-GMR Silicon Laboratories Inc, C8051F336-GMR Datasheet - Page 102

Microcontrollers (MCU) 16KB 10ADC 10DAC 768Ram MCU Lead Free

C8051F336-GMR

Manufacturer Part Number
C8051F336-GMR
Description
Microcontrollers (MCU) 16KB 10ADC 10DAC 768Ram MCU Lead Free
Manufacturer
Silicon Laboratories Inc
Datasheet

Specifications of C8051F336-GMR

Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
16 KB
Data Ram Size
768 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
17
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
QFN-20
3rd Party Development Tools
KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F336DK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
On-chip Dac
10 bit
Package
20QFN
Device Core
8051
Family Name
C8051F336
Maximum Speed
25 MHz
Ram Size
768 Byte
Operating Temperature
-40 to 85 °C
Lead Free Status / Rohs Status
 Details

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C8051F336/7/8/9
17.2. Power-Fail Reset / V
When a power-down transition or power irregularity causes V
monitor will drive the RST pin low and hold the CIP-51 in a reset state (see Figure 17.2). When V
to a level above V
memory contents are not altered by the power-fail reset, it is impossible to determine if V
the level required for data retention. If the PORSF flag reads ‘1’, the data may no longer be valid. The V
monitor is enabled after power-on resets. Its defined state (enabled/disabled) is not altered by any other
reset source. For example, if the V
V
Important Note: If the V
is selected as a reset source. Selecting the V
lized may cause a system reset. In some applications, this reset may be undesirable. If this is not desirable
in the application, a delay should be introduced between enabling the monitor and selecting it as a reset
source. The procedure for enabling the V
state is shown below:
1. Enable the V
2. If necessary, wait for the V
3. Select the V
See Figure 17.2 for V
monitor reset. See
istics of the V
102
DD
monitor will still be disabled after the reset.
DD
DD
DD
monitor.
RST
monitor as a reset source (PORSF bit in RSTSRC = ‘1’).
Section “6. Electrical Characteristics” on page 27
monitor (VDMEN bit in VDM0CN = ‘1’).
, the CIP-51 will be released from the reset state. Note that even though internal data
DD
DD
monitor timing; note that the power-on-reset delay is not incurred after a V
monitor is being turned on from a disabled state, it should be enabled before it
DD
monitor to stabilize.
DD
DD
Monitor
monitor is disabled by code and a software reset is performed, the
DD
monitor and configuring it as a reset source from a disabled
DD
monitor as a reset source before it is enabled and stabi-
Rev.1.0
DD
to drop below V
for complete electrical character-
RST
, the power supply
DD
dropped below
DD
returns
DD
DD

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