C8051F336-GMR Silicon Laboratories Inc, C8051F336-GMR Datasheet - Page 111

Microcontrollers (MCU) 16KB 10ADC 10DAC 768Ram MCU Lead Free

C8051F336-GMR

Manufacturer Part Number
C8051F336-GMR
Description
Microcontrollers (MCU) 16KB 10ADC 10DAC 768Ram MCU Lead Free
Manufacturer
Silicon Laboratories Inc
Datasheet

Specifications of C8051F336-GMR

Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
16 KB
Data Ram Size
768 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
17
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
QFN-20
3rd Party Development Tools
KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F336DK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
On-chip Dac
10 bit
Package
20QFN
Device Core
8051
Family Name
C8051F336
Maximum Speed
25 MHz
Ram Size
768 Byte
Operating Temperature
-40 to 85 °C
Lead Free Status / Rohs Status
 Details

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0
19.2. Programmable Internal High-Frequency (H-F) Oscillator
All C8051F336/7/8/9 devices include a programmable internal high-frequency oscillator that defaults as
the system clock after a system reset. The internal oscillator period caPara1n be adjusted via the OSCICL
register as defined by SFR Definition 19.2.
On C8051F336/7/8/9 devices, OSCICL is factory calibrated to obtain a 24.5 MHz base frequency.
The system clock may be derived from the programmed internal oscillator divided by 1, 2, 4, or 8, as
defined by the IFCN bits in register OSCICN. The divide value defaults to 8 following a reset.
19.2.1. Internal Oscillator Suspend Mode
When software writes a logic 1 to SUSPEND (OSCICN.5), the internal oscillator is suspended. If the sys-
tem clock is derived from the internal oscillator, the input clock to the peripheral or CIP-51 will be stopped
until one of the following events occur:
When one of the oscillator awakening events occur, the internal oscillator, CIP-51, and affected peripherals
resume normal operation, regardless of whether the event also causes an interrupt. The CPU resumes
execution at the instruction following the write to SUSPEND.
SFR Definition 19.2. OSCICL: Internal H-F Oscillator Calibration
SFR Address = 0xB3
Name
Reset
Bit
6:0 OSCICL[6:0] Internal Oscillator Calibration Bits.
Type
7
Bit
Port 0 Match Event.
Port 1 Match Event.
Comparator 0 enabled and output is logic 0.
Timer3 Overflow Event.
Unused
Name
R
7
0
Unused. Read = 0; Write = Don’t Care
These bits determine the internal oscillator period. When set to 0000000b, the H-F
oscillator operates at its fastest setting. When set to 1111111b, the H-F oscillator
operates at its slowest setting. The reset value is factory calibrated to generate an
internal oscillator frequency of 24.5 MHz.
Varies
6
Varies
5
Varies
Rev.1.0
4
OSCICL[6:0]
Function
Varies
R/W
3
C8051F336/7/8/9
Varies
2
Varies
1
Varies
0
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