C8051F336-GMR Silicon Laboratories Inc, C8051F336-GMR Datasheet - Page 146

Microcontrollers (MCU) 16KB 10ADC 10DAC 768Ram MCU Lead Free

C8051F336-GMR

Manufacturer Part Number
C8051F336-GMR
Description
Microcontrollers (MCU) 16KB 10ADC 10DAC 768Ram MCU Lead Free
Manufacturer
Silicon Laboratories Inc
Datasheet

Specifications of C8051F336-GMR

Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
16 KB
Data Ram Size
768 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
17
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
QFN-20
3rd Party Development Tools
KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F336DK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
On-chip Dac
10 bit
Package
20QFN
Device Core
8051
Family Name
C8051F336
Maximum Speed
25 MHz
Ram Size
768 Byte
Operating Temperature
-40 to 85 °C
Lead Free Status / Rohs Status
 Details

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0
C8051F336/7/8/9
SFR Definition 21.2. SMB0CN: SMBus Control
SFR Address = 0xC0; Bit-Addressable
146
Name
Reset
Bit
Type
7
6
5
4
3
2
1
0
Bit
ARBLOST SMBus Arbitration Lost
TXMODE SMBus Transmit Mode
MASTER SMBus Master/Slave
ACKRQ
Name
MASTER
STO
ACK
STA
SI
R
7
0
Indicator. This read-only bit
indicates when the SMBus is
operating as a master.
Indicator. This read-only bit
indicates when the SMBus is
operating as a transmitter.
SMBus Start Flag.
SMBus Stop Flag.
SMBus Acknowledge
Request.
Indicator.
SMBus Acknowledge.
SMBus Interrupt Flag.
This bit is set by hardware
under the conditions listed in
Table 15.3. SI must be cleared
by software. While SI is set,
SCL is held low and the
SMBus is stalled.
TXMODE
R
6
0
Description
STA
R/W
5
0
STO
R/W
Rev.1.0
4
0
0: SMBus operating in
slave mode.
1: SMBus operating in
master mode.
0: SMBus in Receiver
Mode.
1: SMBus in Transmitter
Mode.
0: No Start or repeated
Start detected.
1: Start or repeated Start
detected.
0: No Stop condition
detected.
1: Stop condition detected
(if in Slave Mode) or pend-
ing (if in Master Mode).
0: No Ack requested
1: ACK requested
0: No arbitration error.
1: Arbitration Lost
0: NACK received.
1: ACK received.
0: No interrupt pending
1
:
Interrupt Pending
ACKRQ
Read
R
3
0
ARBLOST
R
2
0
N/A
N/A
0: No Start generated.
1: When Configured as a
Master, initiates a START
or repeated START.
0: No STOP condition is
transmitted.
1: When configured as a
Master, causes a STOP
condition to be transmit-
ted after the next ACK
cycle.
Cleared by Hardware.
N/A
N/A
0: Send NACK
1: Send ACK
0: Clear interrupt, and initi-
ate next state machine
event.
1: Force interrupt.
ACK
R/W
1
0
Write
R/W
SI
0
0

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