C8051F336-GMR Silicon Laboratories Inc, C8051F336-GMR Datasheet - Page 197

• Manufacturer Part Number: C8051F336-GMR
• Description: Microcontrollers (MCU) 16KB 10ADC 10DAC 768Ram MCU Lead Free
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F336-GMR

• Processor Series: C8051F3x
• Core: 8051
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 16 KB
• Data Ram Size: 768 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN-20
• 3rd Party Development Tools: KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F336DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• On-chip Dac: 10 bit
• Package: 20QFN
• Device Core: 8051
• Family Name: C8051F336
• Maximum Speed: 25 MHz
• Ram Size: 768 Byte
• Operating Temperature: -40 to 85 °C
• Lead Free Status / Rohs Status: Details

24.3.2. 8-bit Timers with Auto-Reload
When T3SPLIT is set, Timer 3 operates as two 8-bit timers (TMR3H and TMR3L). Both 8-bit timers oper-
ate in auto-reload mode as shown in Figure 24.8. TMR3RLL holds the reload value for TMR3L; TMR3RLH
holds the reload value for TMR3H. The TR3 bit in TMR3CN handles the run control for TMR3H. TMR3L is
always running when configured for 8-bit Mode.
Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, the external oscillator clock
source divided by 8, or the internal Low-frequency Oscillator. The Timer 3 Clock Select bits (T3MH and
T3ML in CKCON) select either SYSCLK or the clock defined by the Timer 3 External Clock Select bits
(T3XCLK[1:0] in TMR3CN), as follows:
The TF3H bit is set when TMR3H overflows from 0xFF to 0x00; the TF3L bit is set when TMR3L overflows
from 0xFF to 0x00. When Timer 3 interrupts are enabled, an interrupt is generated each time TMR3H over-
flows. If Timer 3 interrupts are enabled and TF3LEN (TMR3CN.5) is set, an interrupt is generated each
time either TMR3L or TMR3H overflows. When TF3LEN is enabled, software must check the TF3H and
TF3L flags to determine the source of the Timer 3 interrupt. The TF3H and TF3L interrupt flags are not
cleared by hardware and must be manually cleared by software.
External Clock / 8
Internal LFO / 8
T3MH
SYSCLK / 12
0
0
0
0
1
T3XCLK[1:0] TMR3H Clock
T3XCLK[1:0]
00
01
10
11
00
01
11
X
Figure 24.8. Timer 3 8-Bit Mode Block Diagram
SYSCLK
Source
SYSCLK / 12
External Clock / 8
Reserved
Internal LFO
SYSCLK
0
1
1
0
M
H
T
3
M
T
3
L
CKCON
T
M
H
2
M
T
2
L
TR3
M
T
1
M
T
0
S
C
A
1
S
C
A
0
Rev.1.0
TCLK
TCLK
TMR3RLH
TMR3RLL
TMR3H
TMR3L
T3ML
0
0
0
0
1
Reload
Reload
C8051F336/7/8/9
T3XCLK[1:0] TMR3L Clock
00
01
10
11
X
T3XCLK1
T3XCLK0
To ADC
TF3CEN
T3SPLIT
TF3LEN
TF3H
TF3L
TR3
Source
SYSCLK / 12
External Clock / 8
Reserved
Internal LFO
SYSCLK
Interrupt
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