C8051F336-GMR Silicon Laboratories Inc, C8051F336-GMR Datasheet - Page 39

Microcontrollers (MCU) 16KB 10ADC 10DAC 768Ram MCU Lead Free

C8051F336-GMR

Manufacturer Part Number
C8051F336-GMR
Description
Microcontrollers (MCU) 16KB 10ADC 10DAC 768Ram MCU Lead Free
Manufacturer
Silicon Laboratories Inc
Datasheet

Specifications of C8051F336-GMR

Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
16 KB
Data Ram Size
768 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
17
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
QFN-20
3rd Party Development Tools
KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F336DK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
On-chip Dac
10 bit
Package
20QFN
Device Core
8051
Family Name
C8051F336
Maximum Speed
25 MHz
Ram Size
768 Byte
Operating Temperature
-40 to 85 °C
Lead Free Status / Rohs Status
 Details

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0
Input/Output” on page 119
7.2.2. Tracking Modes
Each ADC0 conversion must be preceded by a minimum tracking time in order for the converted result to
be accurate. Refer to
complete. The falling edge of AD0BUSY triggers an interrupt (when enabled) and sets the ADC0 interrupt
flag (AD0INT). Note: When polling for ADC conversion completions, the ADC0 interrupt flag (AD0INT)
should be used. Converted data is available in the ADC0 data registers, ADC0H:ADC0L, when bit AD0INT
is logic 1. Note that when Timer 2 or Timer 3 overflows are used as the conversion source, Low Byte over-
flows are used if Timer 2/3 is in 8-bit mode; High byte overflows are used if Timer 2/3 is in 16-bit mode.
See
Important Note About Using CNVSTR: The CNVSTR input pin also functions as Port pin P0.6. When the
CNVSTR input is used as the ADC0 conversion source, Port pin P0.6 should be skipped by the Digital
Crossbar. To configure the Crossbar to skip P0.6, set to ‘1’ Bit6 in register P0SKIP. See
specifications. The AD0TM bit in register ADC0CN controls the ADC0 track-and-hold mode. In its default
state, the ADC0 input is continuously tracked, except when a conversion is in progress. When the AD0TM
bit is logic 1, ADC0 operates in low-power track-and-hold mode. In this mode, each conversion is preceded
by a tracking period of 3 SAR clocks (after the start-of-conversion signal). When the CNVSTR signal is
used to initiate conversions in low-power tracking mode, ADC0 tracks only when CNVSTR is low; conver-
sion begins on the rising edge of CNVSTR (see Figure 7.2). Tracking can also be disabled (shutdown)
when the device is in low power standby or sleep modes. Low-power track-and-hold mode is also useful
when AMUX settings are frequently changed, due to the settling time requirements described in
“7.2.3. Settling Time Requirements” on page
Section “24. Timers” on page 180
(AD0CM[2:0]=000, 001,010
Figure 7.2. 10-Bit ADC Track and Conversion Example Timing
Timer 1, Timer 3 Overflow
Write '1' to AD0BUSY,
(AD0CM[2:0]=100)
Timer 0, Timer 2,
Section “6. Electrical Characteristics” on page 27
SAR Clocks
AD0TM=1
AD0TM=0
AD0TM=1
AD0TM=0
011, 101)
CNVSTR
for details on Port I/O configuration.
Clocks
Clocks
SAR
SAR
Low Power
or Convert
Low Power
or Convert
Track or
Convert
A. ADC0 Timing for External Trigger Source
Track or Convert
B. ADC0 Timing for Internal Trigger Source
for timer configuration.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Track
40.
Track
Rev.1.0
1 2 3 4 5 6 7 8 9
Convert
Convert
Convert
Convert
C8051F336/7/8/9
10 11 12 13 14
Low Power Mode
for minimum tracking time
Track
Low Power
Mode
Track
Section “20. Port
Section
39

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