C8051F336-GMR Silicon Laboratories Inc, C8051F336-GMR Datasheet - Page 48

• Manufacturer Part Number: C8051F336-GMR
• Description: Microcontrollers (MCU) 16KB 10ADC 10DAC 768Ram MCU Lead Free
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F336-GMR

• Processor Series: C8051F3x
• Core: 8051
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 16 KB
• Data Ram Size: 768 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN-20
• 3rd Party Development Tools: KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F336DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• On-chip Dac: 10 bit
• Package: 20QFN
• Device Core: 8051
• Family Name: C8051F336
• Maximum Speed: 25 MHz
• Ram Size: 768 Byte
• Operating Temperature: -40 to 85 °C
• Lead Free Status / Rohs Status: Details

C8051F336/7/8/9
7.4. ADC0 Analog Multiplexer (C8051F336/8 only)
ADC0 on the C8051F336/8 has two analog multiplexers, referred to collectively as AMUX0.
AMUX0 selects the positive and negative inputs to the ADC. Any of the following may be selected as the
positive input: Port I/O pins, the on-chip temperature sensor, or the positive power supply (V
following may be selected as the negative input: Port I/O pins, V
the negative input, ADC0 operates in Single-ended Mode; all other times, ADC0 operates in Differ-
ential Mode. The ADC0 input channels are selected in the AMX0P and AMX0N registers as described in
SFR Definition 7.9 and SFR Definition 7.10.
Important Note About ADC0 Input Configuration: Port pins selected as ADC0 inputs should be config-
ured as analog inputs, and should be skipped by the Digital Crossbar. To configure a Port pin for analog
input, set to ‘0’ the corresponding bit in register PnMDIN. To force the Crossbar to skip a Port pin, set to ‘1’
the corresponding bit in register PnSKIP. See
I/O configuration details.
48
Figure 7.8. ADC0 Multiplexer Block Diagram
Sensor
Temp
P2.3*
P2.3*
P0.0
P0.0
VREF
GND
VDD
*P2.0-P2.3 Only available as
inputs on QFN24 Packaging
Section “20. Port Input/Output” on page 119
Rev.1.0
AMUX
AMUX
AIN+
AIN-
REF
ADC0
AMX0P
AMX0N
, or GND. When GND is selected as
DD
for more Port
). Any of the