AD9763AST Analog Devices Inc, AD9763AST Datasheet

AD9763AST

Manufacturer Part Number

AD9763AST

Description

IC DAC 10BIT DUAL 125MSPS 48LQFP

Manufacturer

Analog Devices Inc

Series

TxDAC+®r

Datasheet

1.AD9763ASTZ.pdf (44 pages)

Specifications of AD9763AST

Rohs Status

RoHS non-compliant

Settling Time

35ns

Number Of Bits

Data Interface

Parallel

Number Of Converters

Voltage Supply Source

Analog and Digital

Power Dissipation (max)

450mW

Operating Temperature

-40°C ~ 85°C

Mounting Type

Surface Mount

Package / Case

48-LQFP

For Use With

AD9763-EBZ - BOARD EVAL FOR AD9763

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FEATURES

10-/12-/14-bit dual transmit digital-to-analog converters (DACs)

125 MSPS update rate

Excellent SFDR to Nyquist @ 5 MHz output: 75 dBc

Excellent gain and offset matching: 0.1%

Fully independent or single-resistor gain control

Dual-port or interleaved data

On-chip 1.2 V reference

5 V or 3.3 V operation

Power dissipation: 380 mW @ 5 V

Power-down mode: 50 mW @ 5 V

48-lead LQFP

APPLICATIONS

Communications

Base stations

Digital synthesis

Quadrature modulation

3D ultrasound

GENERAL DESCRIPTION

The AD9763/AD9765/AD9767 are dual-port, high speed,

2-channel, 10-/12-/14-bit CMOS DACs. Each part integrates

two high quality TxDAC+® cores, a voltage reference, and digital

interface circuitry into a small 48-lead LQFP. The AD9763/

AD9765/AD9767 offer exceptional ac and dc performance

while supporting update rates of up to 125 MSPS.

The AD9763/AD9765/AD9767 have been optimized for

processing I and Q data in communications applications. The

digital interface consists of two double-buffered latches as well

as control logic. Separate write inputs allow data to be written to

the two DAC ports independent of one another. Separate clocks

control the update rate of the DACs.

A mode control pin allows the AD9763/AD9765/AD9767 to

interface to two separate data ports, or to a single interleaved

high speed data port. In interleaving mode, the input data

stream is demuxed into its original I and Q data and then

latched. The I and Q data is then converted by the two DACs

and updated at half the input data rate.

The GAINCTRL pin allows two modes for setting the full-scale

current (I

independently using two external resistors, or I

DACs can be set by using a single external resistor. See the

Gain Control Mode section for important date code

information on this feature.

Rev. F

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

OUTFS

) of the two DACs. I

OUTFS

for each DAC can be set

OUTFS

Dual TxDAC+ Digital-to-Analog Converters

for both

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

The DACs utilize a segmented current source architecture

combined with a proprietary switching technique to reduce

glitch energy and maximize dynamic accuracy. Each DAC provides

differential current output, thus supporting single-ended or dif-

ferential applications. Both DACs of the AD9763, AD9765, or

AD9767 can be simultaneously updated and can provide a

nominal full-scale current of 20 mA. The full-scale currents

between each DAC are matched to within 0.1%.

The AD9763/AD9765/AD9767 are manufactured on an

advanced, low cost CMOS process. They operate from a single

supply of 3.3 V to 5 V and consume 380 mW of power.

PRODUCT HIGHLIGHTS

WRT1/IQWRT

WRT2/IQSEL

The AD9763/AD9765/AD9767 are members of a pin-

compatible family of dual TxDACs providing 8-, 10-, 12-,

and 14-bit resolution.

Dual 10-/12-/14-Bit, 125 MSPS DACs. A pair of high

performance DACs for each part is optimized for low

distortion performance and provides flexible transmission

of I and Q information.

Matching. Gain matching is typically 0.1% of full scale, and

offset error is better than 0.02%.

Low Power. Complete CMOS dual DAC function operates on

380 mW from a 3.3 V to 5 V single supply. The DAC full-scale

current can be reduced for lower power operation, and a sleep

mode is provided for low power idle periods.

On-Chip Voltage Reference. The AD9763/AD9765/AD9767

each include a 1.20 V temperature-compensated band gap

voltage reference.

Dual 10-/12-/14-Bit Inputs. The AD9763/AD9765/AD9767

each feature a flexible dual-port interface, allowing dual or

interleaved input data.

PORT1

PORT2

10-/12-/14-Bit, 125 MSPS

AD9763/AD9765/AD9767

FUNCTIONAL BLOCK DIAGRAM

DVDD1/

DVDD2

INTERFACE

DIGITAL

MODE

DCOM1/

DCOM2

AVDD

AD9763/

AD9765/

AD9767

Figure 1.

LATCH

ACOM

CLK2/IQ RESET

GENERATOR

REFERENCE

CLK1

DAC

BIAS

www.analog.com

REFIO

FSADJ1

FSADJ2

GAINCTRL

SLEEP

OUTA1

OUTB1

OUTA2

OUTB2

Related parts for AD9763AST

AD9763AST Summary of contents

Page 1

FEATURES 10-/12-/14-bit dual transmit digital-to-analog converters (DACs) 125 MSPS update rate Excellent SFDR to Nyquist @ 5 MHz output: 75 dBc Excellent gain and offset matching: 0.1% Fully independent or single-resistor gain control Dual-port or interleaved data On-chip 1.2 V ...

Page 2

AD9763/AD9765/AD9767 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 3 Specifications ..................................................................................... 5 DC Specifications ......................................................................... 5 Dynamic Specifications ............................................................... 6 Digital Specifications ...

Page 3

REVISION HISTORY Revision History: AD9763/AD9765/AD9767 6/09—Rev Rev. F Replaced Figure 86 to Figure 90 with Figure 86 to Figure 91, Deleted Original Figure 91 to Figure 94 ....................................... 34 1/08—Revision E: Initial Combined Version Revision History: AD9763 1/08—Rev. ...

Page 4

AD9763/AD9765/AD9767 Revision History: AD9767 1/08—Rev Rev. E Combined with AD9763 and AD9765 Data Sheets ....... Universal Changes to Figure 1 .......................................................................... 1 Changes to Features Section............................................................ 1 Changes to Applications Section .................................................... 1 Changes to Timing Diagram Section ...

Page 5

SPECIFICATIONS DC SPECIFICATIONS AVDD = 3 DVDD1 = DVDD2 = 3 MIN MAX Table 1. Parameter RESOLUTION 1 DC ACCURACY Integral Linearity Error (INL 25°C ...

Page 6

AD9763/AD9765/AD9767 DYNAMIC SPECIFICATIONS AVDD = 3 DVDD1 = DVDD2 = 3 MIN MAX doubly terminated, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE Maximum Output Update Rate ...

Page 7

DIGITAL SPECIFICATIONS AVDD = 3 DVDD1 = DVDD2 = 3 MIN MAX Table 3. Parameter DIGITAL INPUTS Logic 1 Voltage @ DVDD1 = DVDD2 = 5 V ...

Page 8

AD9763/AD9765/AD9767 ABSOLUTE MAXIMUM RATINGS Table 4. With Parameter Respect To AVDD ACOM DVDD1, DVDD2 DCOM1/DCOM2 ACOM DCOM1/DCOM2 AVDD DVDD1/DVDD2 MODE, DCOM1/DCOM2 CLK1/IQCLK, CLK2/IQRESET, WRT1/IQWRT, WRT2/IQSEL Digital Inputs DCOM1/DCOM2 ACOM OUTA1 OUTA2 I /I OUTB1 OUTB2 REFIO, FSADJ1, ...

Page 9

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DB9P1 (MSB) 1 PIN 1 DB8P1 2 DB7P1 3 DB6P1 4 DB5P1 5 AD9763 DB4P1 6 TOP VIEW (Not to Scale) DB3P1 7 ...

Page 10

AD9763/AD9765/AD9767 Table 6. Pin Function Descriptions Pin No. AD9763 AD9765 AD9767 14, 13, 14, N 35, 36 15, 21 15, 21 15, 21 16, 22 16, ...

Page 11

TYPICAL PERFORMANCE CHARACTERISTICS AD9763 AVDD = 3 DVDD = 3 unless otherwise noted 5MSPS CLK f = 25MSPS CLK 65MSPS CLK (MHz) ...

Page 12

AD9763/AD9765/AD9767 85 910kHz/10MSPS 80 2.27MHz/25MSPS 75 70 5.91MHz/65MSPS 65 60 –20 –16 –12 –8 A (dBFS) OUT Figure 12. Single-Tone SFDR vs. A OUT 85 5MHz/25MSPS 80 1MHz/5MSPS 75 2MHz/10MSPS 70 65 13MHz/65MSPS 60 55 –20 –16 –12 –8 A ...

Page 13

OUT f = 10MHz OUT 25MHz OUT 40MHz OUT 60MHz OUT 45 –60 –40 – TEMPERATURE (°C) Figure 18. SFDR vs. Temperature @ ...

Page 14

AD9763/AD9765/AD9767 AD9765 AVDD = 3 DVDD = 3 Nyquist, unless otherwise noted 5MSPS CLK f = 25MSPS CLK 65MSPS CLK ...

Page 15

Figure 29. Single-Tone SFDR vs OUT OUT 90 1MHz/5MSPS 85 2MHz/10MSPS 5MHz/25MSPS 13MHz/65MSPS 65 25MHz/125MSPS 60 55 –20 –15 –10 –5 A (dBFS) OUT Figure 30. Single-Tone SFDR ...

Page 16

AD9763/AD9765/AD9767 1MHz OUT 10MHz OUT 25MHz OUT 40MHz 60 OUT 60MHz OUT 50 45 –60 –40 – TEMPERATURE (°C) Figure 35. ...

Page 17

AD9767 AVDD = 3 DVDD = 3 Nyquist, unless otherwise noted 5MSPS CLK f = 25MSPS CLK 80 f CLK 65MSPS CLK 50 1 ...

Page 18

AD9763/AD9765/AD9767 90 910kHz/10MSPS 85 2.27MHz/25MSPS 11.37MHz/125MSPS 65 5.91MHz/65MSPS Figure 46. Single-Tone SFDR vs. A OUT 90 1MHz/5MSPS 85 2MHz/10MSPS 80 75 5MHz/25MSPS 70 65 13MHz/65MSPS –20 –15 –10 A (dBFS) OUT Figure 47. Single-Tone ...

Page 19

OUT 10MHz OUT 25MHz OUT 40MHz OUT 60MHz OUT 50 45 –60 –40 – TEMPERATURE (°C) Figure 52. SFDR ...

Page 20

AD9763/AD9765/AD9767 TERMINOLOGY Linearity Error (Integral Nonlinearity or INL) Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. Differential Nonlinearity (DNL) DNL ...

Page 21

THEORY OF OPERATION FSADJ1 R 1 SET REFIO 2kΩ 0.1µF FSADJ2 R 2 SET 2kΩ 1.2V REF WRT1/ GAINCTRL IQWRT DVDD1/DVDD2 50Ω DCOM1/DCOM2 RETIMED CLOCK OUTPUT* LECROY 9210 PULSE GENERATOR Figure 57. Basic AC Characterization Test Setup for AD9763/AD9765/AD9767, Testing ...

Page 22

AD9763/AD9765/AD9767 The full-scale output current of each DAC is regulated by separate reference control amplifiers and can be set from via an external network connected to the full scale adjust (FSADJ) pin. The external network, ...

Page 23

DAC TRANSFER FUNCTION Both DACs in the AD9763/AD9765/AD9767 provide comple- mentary current outputs, I and I OUTA OUTB full-scale current output (I ) when all bits are high (that is, OUTFS DAC CODE = 1024/4095/16,384 for the AD9763/AD9765/ AD9767, respectively), ...

Page 24

AD9763/AD9765/AD9767 I and I also have a negative and positive voltage OUTA OUTB compliance range that must be adhered to in order to achieve optimum performance. The negative output compliance range of −1 set by the breakdown limits ...

Page 25

Interleaved Mode Timing When the MODE pin is at Logic 0, the AD9763/AD9765/AD9767 operate in interleaved mode (refer to Figure 61). In addition, WRT1 functions as IQWRT, CLK1 functions as IQCLK, WRT2 functions as IQSEL, and CLK2 functions as IQRESET. ...

Page 26

AD9763/AD9765/AD9767 Because the AD9763/AD9765/AD9767 is capable of being clocked up to 125 MSPS, the quality of the clock and data input signals are important in achieving the optimum performance. Operating the AD9763/AD9765/AD9767 with reduced logic swings and a corresponding digital ...

Page 27

I OUTFS Figure 69. I vs. I AVDD OUTFS 35 30 125MSPS 25 100MSPS 20 65MSPS 15 10 25MSPS 5 5MSPS 0 0 0.1 0.2 0 ...

Page 28

AD9763/AD9765/AD9767 APPLYING THE AD9763/AD9765/AD9767 OUTPUT CONFIGURATIONS The following sections illustrate some typical output configurations for the AD9763/AD9765/AD9767, with I 20 mA, unless otherwise noted. For applications requiring the optimum dynamic performance, a differential output configuration is suggested. A differential output ...

Page 29

I OUTA 225Ω AD9763/ AD9765/ AD9767 225Ω I OUTB C OPT 25Ω 25Ω Figure 74. Single-Supply DC Differential-Coupled Circuit SINGLE-ENDED, UNBUFFERED VOLTAGE OUTPUT Figure 75 shows the AD9763/AD9765/AD9767 configured to provide a unipolar output range of approximately ...

Page 30

AD9763/AD9765/AD9767 Note that the data in Figure 77 is given in terms of current out vs. voltage in. Noise on the analog power supply has the effect of modulating the internal current sources and therefore the output current. The voltage ...

Page 31

APPLICATIONS VDSL EXAMPLE APPLICATIONS USING THE AD9765 AND AD9767 Very high frequency digital subscriber line (VDSL) technology is growing rapidly in applications requiring data transfer over relatively short distances. By using quadrature amplitude modulation (QAM) and transmitting the data in ...

Page 32

AD9763/AD9765/AD9767 QUADRATURE AMPLITUDE MODULATION (QAM) EXAMPLE USING THE AD9763 QAM is one of the most widely used digital modulation schemes in digital communications systems. This modulation technique can be found in FDM as well as spread spectrum (that is, CDMA) ...

Page 33

I and Q digital data can be fed into the AD9763 in two ways. In dual-port mode, the digital I information drives one input port, and the digital Q information drives the other input port interpolation filter precedes ...

Page 34

AD9763/AD9765/AD9767 EVALUATION BOARD GENERAL DESCRIPTION The AD9763/AD9765/AD9767-EBZ is an evaluation board for the AD9763/AD9765/AD9767 10-/12-/14-bit dual DAC. Careful attention to layout and circuit design, combined with a prototyping area, allow the user to easily and effectively evaluate the AD9763/AD9765/AD9767 in ...

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