AD5330BRU-REEL7 Analog Devices Inc, AD5330BRU-REEL7 Datasheet - Page 9

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AD5330BRU-REEL7

Manufacturer Part Number
AD5330BRU-REEL7
Description
IC DAC 8BIT SNGL VOUT 20-TSSOP
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD5330BRU-REEL7

Rohs Status
RoHS non-compliant
Settling Time
6µs
Number Of Bits
8
Data Interface
Parallel
Number Of Converters
1
Voltage Supply Source
Single Supply
Power Dissipation (max)
1.25mW
Operating Temperature
-40°C ~ 105°C
Mounting Type
Surface Mount
Package / Case
20-TSSOP

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Table 7. AD5340 Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15 to 24
LDAC
GAIN
DB
DB
BUF
CLR
DB
DB
WR
CS
. .
10
11 2
Mnemonic
DB
DB
BUF
V
V
NC
GND
CS
WR
GAIN
CLR
LDAC
PD
V
DB
9
0
REF
OUT
DD
10
24
15
11
12
1
3
8
9
10
11
0
to DB
9
RESET
Ground reference point for all circuitry on the part.
Gain Control Pin. This controls whether the output range from the DAC is 0 V to V
Description
Parallel Data Input.
Most Significant Bit of Parallel Data Input.
Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered.
Reference Input.
Output of DAC. Buffered output with rail-to-rail operation.
No Connect.
Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.
Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.
Asynchronous active low control input that clears all input registers and DAC registers to zero.
Active low control input that updates the DAC registers with the contents of the input registers.
Power-Down Pin. This active low control pin puts the DAC into power-down mode.
Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a
10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
Ten Parallel Data Inputs.
POWER-ON
REGISTER
RESET
INPUT
Figure 7. AD5340 Functional Block Diagram
REGISTER
DAC
12-BIT
V
DAC
REF
4
Rev. A | Page 9 of 28
BUFFER
AD5340
V
14
POWER-DOWN
DD
LOGIC
PD
13
GND
7
5
V
AD5330/AD5331/AD5340/AD5341
OUT
LDAC
Figure 8. AD5340 Pin Configuration
GAIN
DB
DB
V
V
REF
GND
BUF
CLR
REF
OUT
WR
NC
CS
10
11
or 0 V to 2 × V
10
11
12
1
2
3
4
5
6
7
8
9
(Not to Scale)
AD5340
TOP VIEW
12-BIT
REF
.
24
23
22
21
20
19
18
17
16
15
14
13
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
V
PD
DD
9
8
7
6
5
4
3
2
1
0

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