AD5331BRU Analog Devices Inc, AD5331BRU Datasheet - Page 10

• Manufacturer Part Number: AD5331BRU
• Description: IC DAC 10BIT SNGL VOUT 20TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5331BRU

• Rohs Status: RoHS non-compliant
• Settling Time: 7µs
• Number Of Bits: 10
• Data Interface: Parallel
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 1.25mW
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP

AD5330/AD5331/AD5340/AD5341
Table 8. AD5341 Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13 to 20
HBEN
LDAC
GAIN
BUF
CLR
DB
DB
WR
CS
Mnemonic
HBEN
BUF
V
V
GND
CS
WR
GAIN
CLR
LDAC
PD
V
DB
. .
7
0
REF
OUT
DD
20
13
10
0
2
8
1
6
7
9
to DB
7
RESET
Description
High Byte Enable Pin. This pin is used when writing to the device to determine if data is written to the high
byte register or the low byte register.
Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered.
Reference Input.
Output of DAC. Buffered output with rail-to-rail operation.
Ground reference point for all circuitry on the part.
Active low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.
Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.
Gain Control Pin. This controls whether the output range from the DAC is 0 V to V
Asynchronous active low control input that clears all input registers and DAC registers to zero.
Active low control input that updates the DAC registers with the contents of the input registers.
Power-Down Pin. This active low control pin puts the DAC into power-down mode.
Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a
10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
Eight Parallel Data Inputs. DB
POWER-ON
HIGH BYTE
LOW BYTE
REGISTER
REGISTER
RESET
Figure 9. AD5341 Functional Block Diagram
7
12-BIT
V
DAC
is the MSB of these eight bits.
REF
3
Rev. A | Page 10 of 28
BUFFER
AD5341
V
12
POWER-DOWN
DD
LOGIC
PD
11
GND
5
4
V
OUT
Figure 10. AD5341 Pin Configuration
HBEN
LDAC
GAIN
REF
V
V
GND
BUF
CLR
OUT
REF
WR
CS
or 0 V to 2 × V
10
1
2
3
4
5
6
7
8
9
(Not to Scale)
AD5341
TOP VIEW
10-BIT
REF
.
20
19
18
17
16
15
14
13
12
11
DB
DB
DB
DB
DB
DB
DB
DB
V
PD
DD
7
6
5
4
3
2
1
0