AD5333BRU Analog Devices Inc, AD5333BRU Datasheet - Page 17

• Manufacturer Part Number: AD5333BRU
• Description: IC DAC 10BIT DUAL VOUT 24-TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5333BRU

• Rohs Status: RoHS non-compliant
• Settling Time: 7µs
• Number Of Bits: 10
• Data Interface: Parallel
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 2.25mW
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP

Decoding Multiple AD5332/AD5333/AD5342/AD5343
The CS pin on these devices can be used in applications to decode
a number of DACs. In this application, all DACs in the system
receive the same data and WR pulses, but only the CS to one of
the DACs will be active at any one time, so data will only be
written to the DAC whose CS is low. If multiple AD5343s are
being used, a common HBEN line will also be required to
determine if the data is written to the high-byte or low-byte
register of the selected DAC.
The 74HC139 is used as a 2- to 4-line decoder to address any
of the DACs in the system. To prevent timing errors from
occurring, the enable input should be brought to its inactive
state while the coded address inputs are changing state. Figure 36
shows a diagram of a typical setup for decoding multiple devices
in a system. Once data has been written sequentially to all DACs in
a system, all the DACs can be updated simultaneously using a
common LDAC line. A common CLR line can also be used to
reset all DAC outputs to zero.
AD5332/AD5333/AD5342/AD5343 as a Digitally Program-
mable Window Detector
A digitally programmable upper/lower limit detector using the
two DACs in the AD5332/AD5333/AD5342 is shown in Figure
37. The upper and lower limits for the test are loaded to DACs
A and B which, in turn, set the limits on the CMP04. If a signal
at the V
will indicate the fail condition.
REV. 0
ADDRESS
ENABLE
CODED
HBEN
LDAC
CLR
WR
A1
IN
Figure 36. Decoding Multiple DAC Devices
input is not within the programmed window, an LED
*AD5343 ONLY
1G
1A
1B
74HC139
DGND
V
V
CC
DD
1Y0
1Y1
1Y2
1Y3
A0
HBEN*
WR
LDAC
CLR
CS
AD5332/AD5333/
A0
HBEN*
WR
LDAC
CLR
CS
A0
HBEN*
WR
LDAC
CLR
CS
A0
HBEN*
WR
LDAC
CLR
CS
AD5332/AD5333/
AD5332/AD5333/
AD5332/AD5333/
AD5342/AD5343
AD5342/AD5343
AD5342/AD5343
AD5342/AD5343
INPUTS
INPUTS
INPUTS
INPUTS
DATA
DATA
DATA
DATA
–17–
Note that the AD5343 has only a single reference input. If using
the AD5332, AD5333, or AD5342, both reference inputs must
be connected.
Programmable Current Source
Figure 38 shows the AD5332/AD5333/AD5342/AD5343 used
as the control element of a programmable current source. In this
example, the full-scale current is set to 1 mA. The output volt-
age from the DAC is applied across the current setting resistor
of 4.7 kΩ in series with the 470 Ω adjustment potentiometer,
which gives an adjustment of about ± 5%. Suitable transistors to
place in the feedback loop of the amplifier include the BC107
and the 2N3904, which enable the current source to operate
from a minimum V
mined by the operating characteristics of the transistor. Suitable
amplifiers include the AD820 and the OP295, both having rail-
to-rail operation on their outputs. The current for any digital
input code and resistor value can be calculated as follows:
Where:
G is the gain of the buffer amplifier (1 or 2)
D is the digital equivalent of the digital input code
N is the DAC resolution (8, 10, or 12 bits)
R is the sum of the resistor plus adjustment potentiometer in kΩ
V
AD780/REF192
REF
5V
WITH V
EXT
REF
*ONLY ONE CHANNEL OF V
GND
AD5332/AD5333/AD5342/AD5343
V
*NOT AD5343
Figure 37. Programmable Window Detector
DD
IN
Figure 38. Programmable Current Source
V
= 5V
OUT
0.1 F
V
V
REF
REF
AD5332/AD5333/
A*
B*
I
AD5342
GND
0.1 F
0.1 F
=
SOURCE
10 F
G
V
V
×
DD
V
OUT
REF
OUT
V
AD5332/AD5333/
AD5342/AD5343
V
of 6 V. The operating range is deter-
10 F
B
REF
REF
AND V
V
V
*
DD
IN
GND
V
×
DD
= 5V
OUT
(
2
N
SHOWN
V
OUT
CMP04
D
×
1/2
*
R
)
mA
5V
FAIL
1k
1/6 74HC05
PASS/
FAIL
V
SOURCE
LOAD
4.7k
470
PASS
1k