AD5333BRU Analog Devices Inc, AD5333BRU Datasheet - Page 3

• Manufacturer Part Number: AD5333BRU
• Description: IC DAC 10BIT DUAL VOUT 24-TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5333BRU

• Rohs Status: RoHS non-compliant
• Settling Time: 7µs
• Number Of Bits: 10
• Data Interface: Parallel
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 2.25mW
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP

AC CHARACTERISTICS
Parameter
Output Voltage Settling Time
Slew Rate
Major Code Transition Glitch Energy
Digital Feedthrough
Digital Crosstalk
Analog Crosstalk
DAC-to-DAC Crosstalk
Multiplying Bandwidth
Total Harmonic Distortion
NOTES
1
2
3
Specifications subject to change without notice.
TIMING CHARACTERISTICS
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
NOTES
1
2
3
Specifications subject to change without notice.
REV. 0
Guaranteed by design and characterization, not production tested.
See Terminology section.
Temperature range: B Version: –40°C to +105°C; typical specifications are at 25°C.
Guaranteed by design and characterization, not production tested.
All input signals are specified with tr = tf = 5 ns (10% to 90% of V
See Figure 1.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
timed from a voltage level of (V
AD5332
AD5333
AD5342
AD5343
2
Limit at T
0
0
20
5
4.5
5
5
4.5
5
4.5
20
20
50
20
0
IL
+ V
IH
)/2.
1
MIN
(V
otherwise noted.)
DD
, T
= 2.5 V to 5.5 V. R
1, 2, 3
MAX
Min
(V
B Version
DD
= 2.5 V to 5.5 V, All specifications T
Typ
6
7
8
8
0.7
6
0.5
3
0.5
3.5
200
–70
DD
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
) and
L
3
= 2 k
Max
8
9
10
10
–3–
to GND; C
LDAC
LDAC
DATA,
HBEN
GAIN,
BUF,
CLR
Unit
µs
µs
µs
µs
V/µs
nV-s
nV-s
nV-s
nV-s
nV-s
kHz
dB
WR
CS
A0
2
1
L
1
2
Figure 1. Parallel Interface Timing Diagram
SYNCHRONOUS LDAC UPDATE MODE
ASYNCHRONOUS LDAC UPDATE MODE
= 200 pF to GND; all specifications T
Condition/Comments
CS to WR Setup Time
CS to WR Hold Time
WR Pulsewidth
Data, GAIN, BUF, HBEN Setup Time
Data, GAIN, BUF, HBEN Hold Time
Synchronous Mode. WR Falling to LDAC Falling
Synchronous Mode. LDAC Falling to WR Rising
Synchronous Mode. WR Rising to LDAC Rising
Asynchronous Mode. LDAC Rising to WR Rising
Asynchronous Mode. WR Rising to LDAC Falling
LDAC Pulsewidth
CLR Pulsewidth
Time Between WR Cycles
A0 Setup Time
A0 Hold Time
AD5332/AD5333/AD5342/AD5343
Conditions/Comments
V
1/4 Scale to 3/4 Scale Change (40 H to C0 H)
1/4 Scale to 3/4 Scale Change (100 H to 300 H)
1/4 Scale to 3/4 Scale Change (400 H to C00 H)
1/4 Scale to 3/4 Scale Change (400 H to C00 H)
1 LSB Change Around Major Carry
V
V
MIN
REF
REF
REF
t
1
to T
= 2 V. See Figure 20
= 2 V ± 0.1 V p-p. Unbuffered Mode
= 2.5 V ± 0.1 V p-p. Frequency = 10 kHz
t
6
MAX
t
unless otherwise noted.)
3
t
t
t
t
14
4
7
9
t
t
t
2
t
5
8
15
t
10
t
13
MIN
t
11
to T
t
12
MAX
unless