ADV7127JR240 Analog Devices Inc, ADV7127JR240 Datasheet - Page 12

IC DAC VIDEO 240MHZ 3.3/5 28SOIC

ADV7127JR240

Manufacturer Part Number
ADV7127JR240
Description
IC DAC VIDEO 240MHZ 3.3/5 28SOIC
Manufacturer
Analog Devices Inc
Datasheet

Specifications of ADV7127JR240

Rohs Status
RoHS non-compliant
Settling Time
15ns
Number Of Bits
10
Data Interface
Parallel
Number Of Converters
1
Voltage Supply Source
Single Supply
Power Dissipation (max)
30mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
28-SOIC (7.5mm Width)
ADV7127
CIRCUIT DESCRIPTION AND OPERATION
The ADV7127 contains one 10-bit D/A converter, with one
input channel containing a 10-bit register. A reference amplifier
is also integrated on board the part.
Digital Inputs
Ten bits of data (color information) D0–D9 are latched into the
device on the rising edge of each clock cycle. This data is pre-
sented to the 10-bit DAC and is then converted to an analog
output waveform. See Figure 20.
All these digital inputs are specified to accept TTL logic levels.
Clock Input
The CLOCK input of the ADV7127 is typically the pixel clock
rate of the system. It is also known as the dot rate. The dot rate,
and hence the required CLOCK frequency, will be determined
by the on-screen resolution, according to the following equation:
Horiz Res
Vert Res
Refresh Rate
Retrace Factor = Total Blank Time Factor. This takes into
Dot Rate
The required CLOCK frequency is thus 78.6 MHz.
ANALOG OUTPUTS
DIGITAL INPUTS
Dot Rate = (Horiz Res) (Vert Res)
I
OUT
CLOCK
D0–D9
, I
OUT
Figure 20. Video Data Input/Output
(Retrace Factor)
= Number of Pixels/Line.
= Number of Lines/Frame.
= Horizontal Scan Rate. This is the rate at
= 1024 1024
= 78.6 MHz
which the screen must be refreshed, typically
60 Hz for a noninterlaced system or 30 Hz
for an interlaced system.
account that the display is blanked for a
certain fraction of the total duration of each
frame (e.g., 0.8).
Therefore, if we have a graphics system with
a 1024
60 Hz refresh rate and a retrace factor of 0.8,
then:
1024 resolution, a noninterlaced
60/0.8
DATA
(Refresh Rate)/
–12–
All video data and control inputs are latched into the ADV7127
on the rising edge of CLOCK, as previously described in the
Digital Inputs section. It is recommended that the CLOCK
input to the ADV7127 be driven by a TTL buffer (e.g., 74F244).
Description
Data
WHITE LEVEL
VIDEO
BLACK LEVEL
Power Management
The PSAVE input of the ADV7127 puts the part into standby
mode. It is used to reduce power consumption. When PSAVE
is low, the power may be reduced to approximately 10 mW at
3 V. The ADV7127 in TSSOP package also has a power-down
feature where the entire part, including the voltage reference
circuit, is powered down. In this case, power on the ADV7127
can be reduced to 60 W at 3 V.
Mode
Power-Save
Power-Down Power 60 W at 3 V
Reference Input
The ADV7127 has an on-board voltage reference. The V
pin is normally terminated to V
Alternatively, the part could, if required, be overdriven by an
external 1.23 V reference (AD1580).
A resistance R
determines the amplitude of the output video level according to
the following equation:
Using a variable value of R
for accurate adjustment of the analog output video levels. Use
of a fixed 560
as quoted in the specification page. These values typically
correspond to the RS-343A video waveform values as shown in
Figure 21.
mA
17.61
0
I
I
OUT
OUT
Table I. Video Output Truth Table (RSET = 560
R
0.66
LOAD
V
0
(mA) = 7,968
Figure 21. I
= 37.5
100 IRE
SET
ADV7127 TSSOP
10 mW Typically at 3 V 10 mW Typically at 3 V
Table II. Power Management
R
connected between the R
SET
)
resistor yields the analog output levels
OUT
I
Video
17.62
0
OUT
V
SET
Video Output Waveform
REF
, as shown in Figure 22, allows
(V)/R
AA
through a 0.1 F capacitor.
I
0
17.62 – Video Data
17.62
OUT
SET
( )
ADV7127 SOIC
Not Available
SET
pin and GND
DAC
Input
3FF
000H
WHITE
LEVEL
REV. 0
BLACK
REF
LEVEL
,
(1)

Related parts for ADV7127JR240