ADV7127KR140 Analog Devices Inc, ADV7127KR140 Datasheet - Page 6

IC DAC VIDEO 140MHZ 3.3/5 28SOIC

ADV7127KR140

Manufacturer Part Number
ADV7127KR140
Description
IC DAC VIDEO 140MHZ 3.3/5 28SOIC
Manufacturer
Analog Devices Inc
Datasheet

Specifications of ADV7127KR140

Rohs Status
RoHS non-compliant
Settling Time
15ns
Number Of Bits
10
Data Interface
Parallel
Number Of Converters
1
Voltage Supply Source
Single Supply
Power Dissipation (max)
30mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
28-SOIC (7.5mm Width)
ADV7127–SPECIFICATIONS
5 V TIMING SPECIFICATIONS
Parameter
ANALOG OUTPUTS
CLOCK CONTROL
NOTES
1
2
3
4
5
6
7
8
Specifications subject to change without notice.
5 V/3.3 V DYNAMIC SPECIFICATIONS
Parameter
DAC PERFORMANCE
NOTES
1
2
3
Specifications subject to change without notice.
Timing specifications are measured with input levels of 3.0 V (V
These maximum and minimum specifications are guaranteed over this range.
Temperature range: T
Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition.
Measured from 50% point of full-scale transition to 2% of final value.
Guaranteed by characterization.
f
This power-down feature is only available on the ADV7127 in the TSSOP package.
These max/min specifications are guaranteed by characterization.
TTL input values are for 0 V and 3 V with input rise/fall times 3 ns, measured at the 10% and 90% points. Timing reference points at 50% for inputs and outputs.
Clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. Glitch impulse includes clock and data feedthrough.
CLK
Analog Output Delay, t
Analog Output Rise/Fall Time, t
Analog Output Transition Time, t
Analog Output Skew, t
f
f
f
Data and Control Setup, t
Data and Control Hold, t
Clock Pulsewidth High, t
Clock Pulsewidth Low t
Clock Pulsewidth High t
Clock Pulsewidth Low t
Clock Pulsewidth High t
Clock Pulsewidth Low t
Pipeline Delay, t
PSAVE Up Time, t
PDOWN Up Time, t
Glitch Impulse
Data Feedthrough
Clock Feedthrough
CLK
CLK
CLK
max specification production tested at 125 MHz and 5 V. Limits specified here are guaranteed by characterization.
7
7
7
2, 3
MIN
PD
2, 3
6
2, 3
10
to T
6
11
9
MAX
8
6
6
5
5
5
4
4
4
2
: –40 C to +85 C at 50 MHz and 140 MHz, 0 C to +70 C at 240 MHz.
1
7
4
8
5
1
(V
unless otherwise noted, T
AA
Min
0.5
0.5
0.5
1.5
2.5
1.875
1.875
2.85
2.85
8.0
8.0
1.0
= +5 V
IH
) and 0 V (V
(V
are for T
AA
5%
= (3 V–5.25 V)
Typ
5.5
1.0
15
1
1.1
1.25
1.0
2
320
2
, V
IL
A
–6–
) 0 for both 5 V and 3.3 V supplies.
REF
= +25 C unless otherwise noted, T
Min
= 1.235 V, R
J MAX
1.0
= 110 C)
Max
2
50
140
240
10
1
, V
REF
= 1.235 V, R
SET
= 560
Typ
10
22
33
ns
MHz
MHz
MHz
Clock Cycles
ns
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SET
, C
L
= 560
= 10 pF. All specifications T
J MAX
= 110 C)
, C
L
Max
= 10 pF. All specifications
Condition
50 MHz Grade
140 MHz Grade
240 MHz Grade
f
f
f
f
f
f
MAX
MAX
MAX
MAX
MAX
MAX
= 240 MHz
= 240 MHz
= 140 MHz
= 140 MHz
= 50 MHz
= 50 MHz
MIN
Units
pVs
dB
dB
to T
REV. 0
MAX
3

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