AD5390BST-5 Analog Devices Inc, AD5390BST-5 Datasheet

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AD5390BST-5

Manufacturer Part Number
AD5390BST-5
Description
IC DAC 14BIT I2C 16CH 52-LQFP
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD5390BST-5

Rohs Status
RoHS non-compliant
Design Resources
8 to 16 Channels of Programmable Voltage with Excellent Temperature Drift Performance Using AD5390/1/2 (CN0029) AD5390/91/92 Channel Monitor Function (CN0030)
Settling Time
8µs
Number Of Bits
14
Data Interface
I²C, Serial
Number Of Converters
16
Voltage Supply Source
Single Supply
Power Dissipation (max)
35mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
52-LQFP
For Use With
EVAL-AD5390EBZ - BOARD EVALUATION FOR AD5390

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Quantity:
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FEATURES
AD5390: 16-channel, 14-bit voltage output DAC
AD5391: 16-channel, 12-bit voltage output DAC
AD5392: 8-channel, 14-bit voltage output DAC
Guaranteed monotonic
INL
On-chip 1.25 V/2.5 V, 10 ppm/°C reference
Temperature range: −40°C to +85°C
Rail-to-rail output amplifier
Power-down mode
Package types
User interfaces
Serial SPI-, QSPI-, MICROWIRE-, and DSP-compatible
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
(featuring data readback)
±1 LSB max (AD5391)
±3 LSB max (AD5390-5/AD5392-5)
±4 LSB max (AD5390-3/AD5392-3)
64-lead LFCSP (9 mm × 9 mm)
52-lead LQFP (10 mm × 10 mm)
DCEN/AD1
SCLK/SCL
SYNC/AD0
MON_IN1
MON_IN2
DIN/SDA
SPI/I
RESET
BUSY
SDO
CLR
PD
2
C
DV
DD
INTERFACE
CONTROL
(×3)
LOGIC
V
POWER-ON
MON_OUT
IN
RESET
AD5390
0
MUX
DGND (×3/×4)
V
CONTROL
IN
MACHINE
STATE
LOGIC
15
AND
AV
FUNCTIONAL BLOCK DIAGRAM
DD
14
14
14
14
Single-Supply, 12-/14-Bit Voltage Output
(×2)
INPUT
INPUT
INPUT
INPUT
REG
REG
REG
REG
0
1
6
7
14
14
14
14
14
14
14
14
AGND (×2)
8-/16-Channel, 3 V/5 V, Serial Input,
14
14
14
14
m REG0
m REG1
m REG6
m REG7
c REG0
c REG1
c REG6
c REG7
Figure 1.
DAC_GND (×2)
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
I
Integrated functions
APPLICATIONS
Instrumentation and industrial control
Power amplifier control
Level setting (ATE)
Control systems
Microelectromechanical systems (MEMs)
Variable optical attenuators (VOAs)
Optical transceivers (MSA 300, XFP)
2
×2
14
14
14
14
C-compatible interface
channel monitor
simultaneous output update via LDAC
clear function to user-programmable code
amplifier boost mode to optimize slew rate
user-programmable offset and gain adjust
toggle mode enables square wave generation
thermal monitor
LDAC
REFERENCE
DAC
REG
DAC
REG
DAC
REG
DAC
REG
1.25V/2.5V
0
1
6
7
REF_GND
14
14
14
14
AD5390/AD5391/AD5392
DAC 0
DAC 1
DAC 6
DAC 7
REFOUT/REFIN SIGNAL_GND (×2)
©2009 Analog Devices, Inc. All rights reserved.
R
R
R
R
R
R
R
R
VOUT 2
VOUT 3
VOUT 4
VOUT 5
VOUT 0
VOUT 1
VOUT 6
VOUT 7
VOUT 8
VOUT 15
www.analog.com

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AD5390BST-5 Summary of contents

Page 1

FEATURES AD5390: 16-channel, 14-bit voltage output DAC AD5391: 16-channel, 12-bit voltage output DAC AD5392: 8-channel, 14-bit voltage output DAC Guaranteed monotonic INL ±1 LSB max (AD5391) ±3 LSB max (AD5390-5/AD5392-5) ±4 LSB max (AD5390-3/AD5392-3) On-chip 1.25 V/2 ppm/°C ...

Page 2

AD5390/AD5391/AD5392 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 General Description ......................................................................... 3 Specifications ..................................................................................... 4 AD5390-5/AD5391-5/AD5392-5 Specifications ..................... 4 AD5390-5/AD5391-5/AD5392-5 AC Characteristics............. 6 AD5390-3/AD5391-3/AD5392-3 Specifications ..................... 7 AD5390-3/AD5391-3/AD5392-3 AC ...

Page 3

GENERAL DESCRIPTION The AD5390/AD5391 are complete single-supply, 16-channel, 14-bit and 12-bit DACs, respectively. The AD5392 is a complete single-supply, 8-channel, 14-bit DAC. The devices are available in either a 64-lead LFCSP or a 52-lead LQFP. All channels have an on-chip ...

Page 4

AD5390/AD5391/AD5392 SPECIFICATIONS AD5390-5/AD5391-5/AD5392-5 SPECIFICATIONS 5.5 V; AGND = DGND = 0 V; REFIN = 2.5 V external. All specifications unless otherwise noted. Table 2. Parameter ...

Page 5

Parameter LOGIC INPUTS (SCL, SDA Only Input High Voltage Input Low Voltage Input Leakage Current Input Hysteresis HYST C , Input Capacitance IN Glitch Rejection LOGIC OUTPUTS (BUSY, SDO) ...

Page 6

AD5390/AD5391/AD5392 AD5390-5/AD5391-5/AD5392-5 AC CHARACTERISTICS 5.5 V; AGND = DGND = Table 3. Parameter DYNAMIC PERFORMANCE Output Voltage Settling Time AD5390/AD5392 AD5391 2 Slew rate ...

Page 7

AD5390-3/AD5391-3/AD5392-3 SPECIFICATIONS 5.5 V; AGND = DGND = 0 V; REFIN = 1.25 V external. All specifications unless otherwise noted. Table 4. Parameter ACCURACY Resolution ...

Page 8

AD5390/AD5391/AD5392 Parameter 2 Logic Outputs (BUSY, SDO) Output Low Voltage Output High Voltage High Impedance Leakage Current High Impedance Output Capacitance 2 Logic Output (SDA Output Low Voltage OL Three-State Leakage Current Three-State Output Capacitance POWER REQUIREMENTS AV ...

Page 9

AD5390-3/AD5391-3/AD5392-3 AC CHARACTERISTICS 5.5 V; AGND = DGND = Table 5. Parameter DYNAMIC PERFORMANCE Output Voltage Settling Time AD5390/AD5392 AD5391 2 Slew Rate ...

Page 10

AD5390/AD5391/AD5392 TIMING CHARACTERISTICS SERIAL SPI-, QSPI-, MICROWIRE-, AND DSP-COMPATIBLE INTERFACE 5 2 5.5 V; AGND = DGND = 0 V. All specifications Table 6. 3-Wire Serial ...

Page 11

SCLK SYNC DB23 DIN BUSY 1 LDAC VOUT 1 2 LDAC VOUT CLR t VOUT 1 LDAC ACTIVE DURING BUSY 2 LDAC ACTIVE ...

Page 12

AD5390/AD5391/AD5392 SERIAL INTERFACE 5.5 V; AGND = DGND = 0 V. All specifications Table Serial Interface 2 ...

Page 13

ABSOLUTE MAXIMUM RATINGS Transient currents 100 mA do not cause SCR latch-up 25°C, unless otherwise noted. A Table 8. Parameter AV to AGND DGND DD Digital Inputs to DGND Digital Outputs to ...

Page 14

AD5390/AD5391/AD5392 PIN CONFIGURATON AND FUNCTION DESCRIPTIONS PIN INDICATOR AD5390/ REF_GND 7 8 REFOUT/REFIN AD5391 9 SIGNAL_GND 1 10 DAC_GND 1 TOP VIEW (Not to ...

Page 15

Table 9. Pin Function Descriptions Mnemonic Function VOUT X Buffered Analog Outputs for Channel X. Each analog output is driven by a rail-to-rail output amplifier operating at a gain of 2. Each output is capable of driving an output load ...

Page 16

AD5390/AD5391/AD5392 Mnemonic Function PD Power-Down (level-sensitive, active high). Used to place the device in low power mode, in which the device consumes 1 μA analog current and 20 μA digital current. In power-down mode, all internal analog circuitry is placed ...

Page 17

TERMINOLOGY Relative Accuracy or Endpoint Linearity (INL) A measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function measured after adjusting for zero-scale error and full-scale error and is expressed ...

Page 18

AD5390/AD5391/AD5392 TYPICAL PERFORMANCE CHARACTERISTICS 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0 4096 8192 INPUT CODE Figure 11. AD5390-5/AD5392-5 Typical INL Plot 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0 4096 8192 INPUT CODE Figure 12. ...

Page 19

WR BUSY VREF = 2. 25°C A EXITS SOFT PD TO MIDSCALE Figure 17. AD539x Exiting Soft Power-Down VREF = 2.5V VOUT T A EXITS HARDWARE ...

Page 20

AD5390/AD5391/AD5392 1.254 VREF = 1.25V 1.253 T = 25°C A 14ns/SAMPLE NUMBER 1.252 1 LSB CHANGE AROUND MIDSCALE GLITCH IMPULSE = 5nV-s 1.251 1.250 1.249 1.248 1.247 1.246 1.245 0 50 100 150 ...

Page 21

25°C A DAC LOADED WITH MIDSCALE EXTERNAL REFERENCE Y AXIS = 5µV/DIV X AXIS = 100ms/DIV Figure 29. 0 Output Noise Plot AD5390/AD5391/AD5392 ...

Page 22

AD5390/AD5391/AD5392 FUNCTIONAL DESCRIPTION DAC ARCHITECTURE The AD5390/AD5391 are complete single-supply, 16-channel, voltage output DACs offering a resolution of 14 bits and 12 bits, respectively. The AD5392 is a complete single-supply, 8-channel, voltage output DAC offering 14-bit resolution. All devices are ...

Page 23

DATA DECODING AD5390/AD5392 The AD5390/AD5392 contain an internal 14-bit data bus. The input data is decoded depending on the data loaded to the REG1 and REG0 bits of the input serial register. This is shown in Table 10. Data from ...

Page 24

AD5390/AD5391/AD5392 INTERFACES The AD5390/AD5391/AD5392 contain a serial interface that can be programmed to be DSP-, SPI-, and MICROWIRE- 2 compatible C-compatible. The SPI/ I the interface mode. To minimize both the power consumption of the device and the ...

Page 25

Standalone Mode By connecting the daisy-chain enable (DCEN) pin low, stand- alone mode is enabled. The serial interface works with both a continuous and a noncontinuous serial clock. The first falling edge of SYNC starts the write cycle and resets ...

Page 26

AD5390/AD5391/AD5392 SERIAL INTERFACE The AD5390/AD5391/AD5392 feature an I 2-wire interface consisting of a serial data line (SDA) and a serial clock line (SCL). SDA and SCL facilitate communication between the DACs and the master at rates up ...

Page 27

I C WRITE OPERATION There are three specific modes in which data can be written to the AD539x family of DACs. 4-BYTE MODE When writing to the AD539x DACs, begin with an address byte ( 0), after ...

Page 28

AD5390/AD5391/AD5392 3-BYTE MODE The 3-byte mode lets the user update more than one channel in a write sequence without having to write the device address byte each time. The device address byte is required only once and subsequent channel updates ...

Page 29

MODE The 2-byte mode lets the user update channels sequentially following initialization of this mode. The device address byte is required only once and the address pointer is configured for autoincrement or burst mode. The user must begin with ...

Page 30

AD5390/AD5391/AD5392 AD539x ON-CHIP SPECIAL FUNCTION REGISTERS The AD539x family of parts contains a number of special function registers (SFRs) as shown in Table 22. SFRs are addressed with REG1 = 0 and REG0 = 0 and are decoded using Address ...

Page 31

Table 23. AD5390/AD5392 Channel Monitor Decoding REG1 REG0 ...

Page 32

AD5390/AD5391/AD5392 CONTROL REGISTER WRITE Table 25 shows the control register contents for the AD5390 and the AD5392. Table 26 provides bit descriptions. Note that REG1 = REG0 = 1100, and DB13 to DB0 contain the ...

Page 33

Table 27 shows the control register contents of the AD5391. Table 28 provides bit descriptions. Note that REG1 = REG0 = 1100, and DB13 to DB0 contain the control register data. Table 27. AD5391 Control ...

Page 34

AD5390/AD5391/AD5392 HARDWARE FUNCTIONS RESET FUNCTION Bringing the RESET line low resets the contents of all internal registers to their power-on reset state. RESET is a negative edge- sensitive input. The default corresponds full scale and c at ...

Page 35

AD539x to PIC16C6x/7x The PIC16C6x/7x synchronous serial port (SSP) is configured as an SPI master with the clock polarity bit = 0. This is done by writing to the synchronous serial port control register (SSPCON)—see the PIC16/17 Microcontroller User Manual. ...

Page 36

AD5390/AD5391/AD5392 APPLICATION INFORMATION POWER SUPPLY DECOUPLING In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD539x is mounted should ...

Page 37

AD539x MONITOR FUNCTION The AD5390 contains a channel monitor function consisting of a multiplexer addressed via the interface, allowing any channel output to be routed to this pin for monitoring using an external ADC. The channel monitor function must be ...

Page 38

AD5390/AD5391/AD5392 12- and 14-bit resolution. Figure 45 shows a typical transmitter architecture, in which the AD539x DACs can be used in the following control circuits: I control, average power control BIAS (APC), peak power control (PPC), transmit gain control (TGC), ...

Page 39

OUTLINE DIMENSIONS PIN 1 INDICATOR TOP VIEW 12° MAX 1.00 0.85 0.80 SEATING PLANE 1.45 1.40 1.35 0.15 SEATING 0.05 PLANE VIEW A ROTATED 90° CCW 9.00 BSC SQ 0.60 MAX 49 48 0.50 8.75 BSC BSC SQ 0.50 0.40 ...

Page 40

... AD5390BCPZ-5-REEL −40°C to +85°C 1 AD5390BCPZ-5-REEL7 −40°C to +85°C 1 AD5390BSTZ-3 −40°C to +85°C 1 AD5390BSTZ-5 −40°C to +85°C AD5391BCP-3 −40°C to +85°C AD5391BCP-3-REEL −40°C to +85°C AD5391BCP-3-REEL7 −40°C to +85°C 1 AD5391BCPZ-3 −40°C to +85°C AD5391BCP-5 − ...

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