AD5381BST-3 Analog Devices Inc, AD5381BST-3 Datasheet

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AD5381BST-3

Manufacturer Part Number
AD5381BST-3
Description
IC DAC 12BIT 40CH 3V 100-LQFP
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD5381BST-3

Design Resources
40 Channels of Programmable Voltage with Excellent Temperature Drift Performance Using AD5381 (CN0010) AD5381 Channel Monitor Function (CN0013)
Settling Time
6µs
Number Of Bits
12
Data Interface
Serial, Parallel
Number Of Converters
40
Voltage Supply Source
Single Supply
Power Dissipation (max)
80mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-LQFP
For Use With
EVAL-AD5381EB - BOARD EVAL FOR AD5381
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
FEATURES
Guaranteed monotonic
INL error: ±1 LSB max
On-chip 1.25 V/2.5 V, 10 ppm/°C reference
Temperature range: –40°C to +85°C
Rail-to-rail output amplifier
Power-down
Package type: 100-lead LQFP (14 mm × 14 mm)
User interfaces:
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
Parallel
Serial (SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible,
I
DB10/(SCLK/SCL)
2
WR/(DCEN/AD1)
DB11/(DIN/SDA)
C®-compatible
CS/(SYNC/AD0)
featuring data readback)
DB9/(SPI/I
SER/PAR
FIFO EN
RESET
REG0
REG1
BUSY
SDO
CLR
DB8
DB0
2
PD
A5
A0
C)
VOUT0………VOUT38
VOUT39/MON_OUT
INTERFACE
POWER-ON
DVDD (×3)
CONTROL
39-TO-1
RESET
LOGIC
MUX
AD5381
CONTROL
MACHINE
STATE
LOGIC
DGND (×3)
FIFO
+
+
12
12
12
12
AVDD (×5)
FUNCTIONAL BLOCK DIAGRAM
INPUT
INPUT
INPUT
INPUT
REG0
REG1
REG6
REG7
12
12
12
12
12
12
12
12
12
12
12
12
AGND (×5)
m REG0
m REG1
m REG6
m REG7
c REG0
c REG1
c REG6
c REG7
×5
Figure 1.
40-Channel, 3 V/5 V, Single-Supply,
DAC_GND (×5)
INTEGRATED FUNCTIONS
Channel monitor
Simultaneous output update via LDAC
Clear function to user-programmable code
Amplifier boost mode to optimize slew rate
User-programmable offset and gain adjust
Toggle mode enables square wave generation
Thermal monitors
APPLICATIONS
Variable optical attenuators (VOAs)
Level setting (ATE)
Optical micro-electro-mechanical systems (MEMs)
Control systems
Instrumentation
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
12
12
12
12
12-Bit, Voltage Output DAC
LDAC
REG0
REG1
REG6
REG7
DAC
DAC
DAC
DAC
REFGND
12
12
12
12
REFERENCE
1.25V/2.5V
DAC 0
DAC 1
DAC 6
DAC 7
© 2005 Analog Devices, Inc. All rights reserved.
REFOUT/REFIN
R
R
R
R
SIGNAL_GND (×5)
R
R
R
R
www.analog.com
AD5381
VOUT0
VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6
VOUT7
VOUT8
VOUT38

Related parts for AD5381BST-3

AD5381BST-3 Summary of contents

Page 1

FEATURES Guaranteed monotonic INL error: ±1 LSB max On-chip 1.25 V/2 ppm/°C reference Temperature range: –40°C to +85°C Rail-to-rail output amplifier Power-down Package type: 100-lead LQFP (14 mm × 14 mm) User interfaces: Parallel Serial (SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible, featuring data ...

Page 2

AD5381 TABLE OF CONTENTS General Description ......................................................................... 3 Specifications..................................................................................... 4 AD5381-5 Specifications ............................................................. 4 AD5381-3 Specifications ............................................................. 6 AC Characteristics........................................................................ 7 Timing Characteristics..................................................................... 8 Serial Interface Timing ................................................................ Serial Interface Timing........................................................ 10 Parallel Interface Timing ........................................................... ...

Page 3

GENERAL DESCRIPTION The AD5381 is a complete, single-supply, 40-channel, 12-bit DAC available in a 100-lead LQFP package. All 40 channels have an on-chip output amplifier with rail-to-rail operation. The AD5381 includes a programmable internal 1.25 V/2 ppm/°C reference, ...

Page 4

AD5381 SPECIFICATIONS AD5381-5 SPECIFICATIONS AVDD = 4 5.5 V; DVDD = 2 5.5 V, AGND = DGND = 0 V; external REFIN = 2.5 V; all specifications T unless otherwise noted. Table 3. Parameter ACCURACY Resolution ...

Page 5

Parameter LOGIC INPUTS (SDA, SCL ONLY Input High Voltage Input Low Voltage Input Leakage Current Input Hysteresis HYST C , Input Capacitance IN Glitch Rejection 3 LOGIC OUTPUTS (BUSY, ...

Page 6

AD5381 AD5381-3 SPECIFICATIONS AVDD = 2 3.6 V; DVDD = 2 5.5 V, AGND = DGND = 0 V; external REFIN = 1.25 V; all specifications unless otherwise noted. MIN MAX Table ...

Page 7

Parameter 3 LOGIC OUTPUTS (BUSY, SDO Output Low Voltage Output High Voltage OH High Impedance Leakage Current High Impedance Output Capacitance LOGIC OUTPUT (SDA Output Low Voltage OL Three-State Leakage Current Three-State ...

Page 8

AD5381 TIMING CHARACTERISTICS SERIAL INTERFACE TIMING DVDD = 2 5.5 V; AVDD 3.6 V; AGND = DGND = 0 V; all specifications unless otherwise noted. ...

Page 9

SCLK SYNC DIN DB23 BUSY 1 LDAC VOUT1 2 LDAC VOUT2 t 18 CLR VOUT 1 LDAC ACTIVE DURING BUSY. 2 LDAC ACTIVE AFTER BUSY. Figure 3. Serial Interface ...

Page 10

AD5381 SERIAL INTERFACE TIMING DVDD = 2 5.5 V; AVDD = 3.6 V; AGND = DGND = 0 V; all specifications T unless otherwise noted. Table ...

Page 11

PARALLEL INTERFACE TIMING DVDD = 2 5.5 V; AVDD = 3.6 V; AGND = DGND = 0 V; all specifications T unless otherwise noted. Table ...

Page 12

AD5381 REG0, REG1, A5...A0 DB11...DB0 BUSY LDAC VOUT1 LDAC VOUT2 CLR VOUT ...

Page 13

ABSOLUTE MAXIMUM RATINGS 25°C, unless otherwise noted. A Table 9. Parameter Rating AVDD to AGND –0 DVDD to DGND –0 Digital Inputs to DGND –0 DVDD + ...

Page 14

AD5381 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS FIFO EN 1 CLR 2 VOUT24 3 VOUT25 4 VOUT26 5 VOUT27 6 7 SIGNAL_GND4 8 DAC_GND4 AGND4 9 AVDD4 10 VOUT28 11 VOUT29 12 VOUT30 13 VOUT31 14 REFGND 15 REFOUT/REFIN 16 17 ...

Page 15

Mnemonic Function REFOUT/REFIN The AD5381 contains a common REFOUT/REFIN pin. When the internal reference is selected, this pin is the reference output. If the application requires an external reference, it can be applied to this pin and the internal reference ...

Page 16

AD5381 Mnemonic Function PD Power-Down (Level Sensitive, Active High used to place the device in low power mode, where the analog current consumption is reduced to 2 μA and the digital current consumption is reduced to 20 μA. ...

Page 17

TERMINOLOGY Relative Accuracy Relative accuracy, or endpoint linearity measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function measured after adjusting for zero-scale error and full-scale error, and ...

Page 18

AD5381 TYPICAL PERFORMANCE CHARACTERISTICS 1.00 0.75 0.50 0.25 0 –0.25 –0.50 –0.75 –1.00 0 512 1024 1536 2048 2560 INPUT CODE Figure 9. Typical AD5381-5 INL Plot 2.539 AVDD = DVDD = 5V 2.538 V = 2.5V REF 2.537 T ...

Page 19

AI (mA) DD Figure 15. AI Histogram with Boost Off 0.4 0.5 0.6 0.7 0.8 DI (mA) DD Figure 16. DI Histogram DD ...

Page 20

AD5381 6 FULL SCALE 5 AVDD = DVDD = 5V 3/4 SCALE 4 MIDSCALE 3 2 1/4 SCALE 1 ZERO SCALE 0 –1 –40 –20 –10 –5 – CURRENT (mA) Figure 21. AD5381-5 Output Amplifier Source and Sink ...

Page 21

FUNCTIONAL DESCRIPTION DAC ARCHITECTURE—GENERAL The AD5381 is a complete, single-supply, 40-channel voltage output DAC that offers 12-bit resolution. The part is available in a 100-lead LQFP package and features both a parallel and a serial interface. This product includes an ...

Page 22

AD5381 ON-CHIP SPECIAL FUNCTION REGISTERS (SFR) The AD5381 contains a number of special function registers (SFRs), as outlined in Table 15. SFRs are addressed with REG1 = REG0 = 0 and are decoded using Address Bits A5 to A0. Table ...

Page 23

Table 16. Control Register Contents MSB CR11 CR10 CR9 CR8 Control Register Write/Read REG1 = REG0 = 001100 status determines if the operation is a write ( read ...

Page 24

AD5381 Table 18. AD5381 Channel Monitor Decoding REG1 REG0 ...

Page 25

HARDWARE FUNCTIONS RESET FUNCTION Bringing the RESET line low resets the contents of all internal registers to their power-on reset state. Reset is a negative edge- sensitive input. The default corresponds full-scale and zero ...

Page 26

AD5381 INTERFACES The AD5381 contains both parallel and serial interfaces. Furthermore, the serial interface can be programmed either SPI-, DSP-, MICROWIRE C-compatible. The SER/ PAR pin selects parallel and serial interface modes serial ...

Page 27

Daisy-Chain Mode For systems that contain several devices, the SDO pin can be used to daisy-chain several devices together. This daisy-chain mode can be useful in system diagnostics and in reducing the number of serial interface lines. By connecting the ...

Page 28

AD5381 SERIAL INTERFACE 2 The AD5381 features an I C-compatible 2-wire interface consisting of a serial data line (SDA) and a serial clock line (SCL). SDA and SCL facilitate communication between the AD5381 and the master at ...

Page 29

SCL SDA START COND BY MASTER ADDRESS BYTE SCL REG1 REG0 MSB SDA MOST SIGNIFICANT BYTE SCL SDA START COND BY MASTER ADDRESS BYTE SCL SDA REG1 REG0 MSB MOST ...

Page 30

AD5381 2-Byte Mode Following initialization of 2-byte mode, the user can update channels sequentially. The device address byte is only required once and the pointer address pointer is configured for auto- increment or burst mode. The user must begin with ...

Page 31

MICROPROCESSOR INTERFACING Parallel Interface The AD5381 can be interfaced to a variety of 16-bit microcon- trollers or DSP processors. Figure 35 shows the AD5381 family interfaced to a generic 16-bit microcontroller/DSP processor. The lower address lines from the processor are ...

Page 32

AD5381 AD5381 to PIC16C6x/7x The PIC16C6x/7x synchronous serial port (SSP) is configured as an SPI master with the Clock Polarity Bit = 0. This is done by writing to the synchronous serial port control register (SSPCON). See the PIC16/17 microcontroller ...

Page 33

APPLICATION INFORMATION POWER SUPPLY DECOUPLING In any circuit where accuracy is important, careful considera- tion of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5381 is mounted should ...

Page 34

AD5381 MONITOR FUNCTION The AD5381 channel monitor function consists of a multiplexer addressed via the interface, allowing any channel output to be routed to this pin for monitoring using an external ADC. In channel monitor mode, VOUT39 becomes the MON_OUT ...

Page 35

INPUT INPUT DATA REGISTER A/B OPTICAL ATTENUATORS Based on its high channel count, high resolution, monotonic behavior, and high level of integration, the AD5381 is ideally targeted at optical attenuation applications used in dynamic gain equalizers, variable optical attenuators (VOAs), ...

Page 36

AD5381 GROUP A GROUP B GROUP C CHNLS 0–39 CHNLS 40–79 CHNLS 80–119 FIFO DATA LOAD GROUP A FIFO DATA LOAD 1.6μs 1.6μs GROUP B OUTPUT UPDATE 14.4μs TIME FOR GROUP A 14.4μs GROUP D GROUP E GROUP F GROUP ...

Page 37

... OUTLINE DIMENSIONS 1.45 1.40 1.35 0.15 SEATING 0.05 PLANE VIEW A ROTATED 90° CCW ORDERING GUIDE Model Resolution AD5381BST-3 12 Bits AD5381BST-3-REEL 12 Bits 1 AD5381BSTZ-3 12 Bits 1 AD5381BSTZ-3-REEL 12 Bits AD5381BST-5 12 Bits AD5381BST-5-REEL 12 Bits 1 AD5381BSTZ-5 12 Bits 1 AD5381BSTZ-5-REEL 12 Bits EVAL-AD5381EB Pb-free part Standard Specification as defined by Philips. 1.60 MAX ...

Page 38

AD5381 NOTES Rev Page ...

Page 39

NOTES Rev Page AD5381 ...

Page 40

AD5381 NOTES Purchase of licensed components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I 2 Rights to use these components system, ...

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