AD5383BST-3 Analog Devices Inc, AD5383BST-3 Datasheet
AD5383BST-3
Specifications of AD5383BST-3
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AD5383BST-3 Summary of contents
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FEATURES Guaranteed monotonic INL error: ±1 LSB max On-chip 1.25 V/2 ppm/°C reference Temperature range: –40°C to +85°C Rail-to-rail output amplifier Power-down mode Package type: 100-lead LQFP (14 mm × 14 mm) User Interfaces Parallel Serial (SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible, featuring ...
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AD5383 TABLE OF CONTENTS General Description ......................................................................... 3 Specifications ..................................................................................... 4 AD5383-5 Specifications ............................................................. 4 AD5383-3 Specifications ............................................................. 6 AC Characteristics ........................................................................ 7 Timing Characteristics ..................................................................... 8 Serial Interface Timing ................................................................ Serial Interface Timing ........................................................ 10 ...
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GENERAL DESCRIPTION The AD5383 is a complete, single-supply, 32-channel, 12-bit DAC available in a 100-lead LQFP package. All 32 channels have an on-chip output amplifier with rail-to-rail operation. The AD5383 includes a programmable internal 1.25 V/2 ppm/°C reference; ...
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AD5383 SPECIFICATIONS AD5383-5 SPECIFICATIONS 5.5 V, AGND = DGND = 0 V; external REFIN = 2.5 V; all specifications otherwise noted. Table 3. Parameter ACCURACY ...
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Parameter LOGIC OUTPUTS ( BUSY , SDO Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage OH High Impedance Leakage Current High Impedance Output Capacitance ...
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AD5383 AD5383-3 SPECIFICATIONS 5.5 V, AGND = DGND = 0 V; external REFIN = 1.25 V; all specifications otherwise noted. Table 4. Parameter ACCURACY Resolution ...
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Parameter 3 LOGIC OUTPUTS (BUSY, SDO Output Low Voltage Output High Voltage OH High Impedance Leakage Current High Impedance Output Capacitance 3 LOGIC OUTPUT (SDA Output Low Voltage OL Three-State Leakage Current Three-State ...
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AD5383 TIMING CHARACTERISTICS SERIAL INTERFACE TIMING 3.6 V; AGND = DGND = 0 V; all specifications noted. Table 6. ...
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SCLK SYNC DIN DB23 BUSY 1 LDAC 1 V OUT 2 LDAC 2 V OUT t 18 CLR V OUT 1 LDAC ACTIVE DURING BUSY 2 LDAC ACTIVE ...
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AD5383 SERIAL INTERFACE TIMING 3.6 V; AGND = DGND = 0 V; all specifications noted. Table ...
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PARALLEL INTERFACE TIMING 3.6 V; AGND = DGND = 0 V; all specifications noted. Table ...
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AD5383 REG0, REG1, A4..A0 DB11..DB0 BUSY LDAC V OUT LDAC V OUT CLR ...
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ABSOLUTE MAXIMUM RATINGS 25°C, unless otherwise noted . A Table 9. Parameter Rating AV to AGND –0 DGND –0 Digital Inputs to DGND –0.3 V ...
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AD5383 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS FIFO EN 1 CLR OUT OUT OUT OUT SIGNAL_GND4 7 DAC_GND4 8 AGND4 ...
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Mnemonic Function MON_OUT MON_OUT Monitor Output Pin. When the monitor function is enabled, this output acts as the output of a 36-to-1 channel multiplexer that can be programmed to multiplex one of Channels 0 to 31or any of the monitor ...
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AD5383 Mnemonic Function PD Power Down (Level Sensitive, Active High used to place the device in low power mode where the device consumes 2 μA analog supply current and 20 μA digital supply current. In power-down mode, all ...
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TERMINOLOGY Relative Accuracy Relative accuracy, or endpoint linearity measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function measured after adjusting for zero-scale error and full-scale error, and ...
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AD5383 TYPICAL PERFORMANCE CHARACTERISTICS 1.00 0.75 0.50 0.25 0 –0.25 –0.50 –0.75 –1.00 0 512 1024 1536 2048 2560 INPUT CODE Figure 9. Typical AD5383-5 INL Plot 2.539 2.538 V = 2.5V REF ...
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AI (mA) DD Figure 15. AI Histogram 0.4 0.5 0.6 0.7 0.8 DI (mA) DD Figure 16. DI Histogram DD WR BUSY AV ...
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AD5383 6 FULL-SCALE 5 AV 3/4 SCALE 4 MIDSCALE 3 2 1/4 SCALE 1 ZERO-SCALE 0 –1 –40 –20 –10 –5 – CURRENT (mA) Figure 21. AD5383-5 Output Amplifier Source and Sink Capability 0.20 0.15 0.10 ERROR AT ...
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FUNCTIONAL DESCRIPTION DAC ARCHITECTURE—GENERAL The AD5383 is a complete, single-supply, 32-channel voltage output DAC that offers 12-bit resolution. The part is available in a 100-lead LQFP package and features both a parallel and a serial interface. This product includes an ...
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AD5383 ON-CHIP SPECIAL FUNCTION REGISTERS (SFR) The AD5383 contains a number of special function registers (SFRs), as outlined in Table 15. SFRs are addressed with REG1 = REG0 = 0 and are decoded using Address Bit A4 to Address Bit ...
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Table 16. Control Register Contents MSB CR11 CR10 CR9 CR8 Control Register Write/Read REG1 = REG0 = 01100 status determines if the operation is a write ( read ...
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AD5383 Table 18. Channel Monitor Decoding REG1 REG0 ...
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HARDWARE FUNCTIONS RESET FUNCTION Bringing the RESET line low resets the contents of all internal registers to their power-on reset state. RESET is a negative edge- sensitive input. The default corresponds full scale and ...
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AD5383 INTERFACES The AD5383 contains both parallel and serial interfaces. Furthermore, the serial interface can be programmed C-compatible. The SER/ PAR SPI-, DSP-, MICROWIRE pin selects parallel and serial interface modes. In serial mode, the ...
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Daisy-Chain Mode For systems that contain several devices, the SDO pin may be used to daisy-chain several devices together. This daisy-chain mode can be useful in system diagnostics and in reducing the number of serial interface lines. By connecting the ...
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AD5383 SERIAL INTERFACE 2 The AD5383 features an I C-compatible, 2-wire interface consisting of a serial data line (SDA) and a serial clock line (SCL). SDA and SCL facilitate communication between the AD5383 and the master at ...
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SCL SDA START COND BY MASTER ADDRESS BYTE SCL REG1 REG0 MSB SDA MOST SIGNIFICANT BYTE SCL SDA START COND BY MASTER ADDRESS BYTE SCL SDA REG1 REG0 MSB MOST ...
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AD5383 2-Byte Mode Following initialization of 2-byte mode, the user can sequentially update channels. The device address byte is only required once, and the address pointer is configured for auto- increment or burst mode. The user must begin with an ...
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MICROPROCESSOR INTERFACING Parallel Interface The AD5383 can be interfaced to a variety of 16-bit microcon- trollers or DSP processors. Figure 35 shows the AD5383 family interfaced to a generic 16-bit microcontroller/DSP processor. The lower address lines from the processor are ...
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AD5383 AD5383 to PIC16C6x/7x The PIC16C6x/7x synchronous serial port (SSP) is configured as an SPI master with the clock polarity bit = 0. This is done by writing to the synchronous serial port control register (SSPCON). See the PIC16/17 Microcontroller ...
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APPLICATION INFORMATION POWER SUPPLY DECOUPLING In any circuit where accuracy is important, careful considera- tion of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5383 is mounted should ...
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AD5383 CHANNEL MONITOR FUNCTION The AD5383 contains a channel monitor function that consists of a multiplexer addressed via the interface, allowing any chan- nel output to be routed to this pin for monitoring using an external ADC. The channel monitor ...
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INPUT INPUT DATA REGISTER A/B DWDM IN FIBRE AWG OPTICAL ATTENUATORS Based on its high channel count, high resolution, monotonic behavior, and high level of integration, the AD5383 is ideally targeted at optical attenuation applications used in dynamic gain equalizers, ...
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AD5383 UTILIZING THE FIFO The AD5383 FIFO mode optimizes total system update rates in applications where a large number of channels need to be updated. FIFO mode is only available when parallel interface mode is selected. The FIFO EN pin ...
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... OUTLINE DIMENSIONS 1.45 1.40 1.35 0.15 SEATING 0.05 PLANE VIEW A ROTATED 90° CCW ORDERING GUIDE 1 Model Resolution AD5383BSTZ-3 12 Bits AD5383BSTZ-5 12 Bits RoHS Compliant Part. 16.20 16.00 SQ 1.60 MAX 15.80 0.75 100 1 0.60 0.45 PIN 1 (PINS DOWN) 0.20 0.09 7° 3.5° ...
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AD5383 NOTES Rev Page ...
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NOTES Rev Page AD5383 ...
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AD5383 NOTES refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2004–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03734–0–4/10(B) Rev ...