AD5383BST-3 Analog Devices Inc, AD5383BST-3 Datasheet

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AD5383BST-3

Manufacturer Part Number
AD5383BST-3
Description
IC DAC 12BIT 32CH 3V 100-LQFP
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD5383BST-3

Design Resources
32 Channels of Programmable Voltage with Excellent Temperature Drift Performance Using AD5383 (CN0014) AD5383 Channel Monitor Function (CN0015)
Settling Time
6µs
Number Of Bits
12
Data Interface
Serial, Parallel
Number Of Converters
32
Voltage Supply Source
Single Supply
Power Dissipation (max)
39mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
FEATURES
Guaranteed monotonic
INL error: ±1 LSB max
On-chip 1.25 V/2.5 V, 10 ppm/°C reference
Temperature range: –40°C to +85°C
Rail-to-rail output amplifier
Power-down mode
Package type: 100-lead LQFP (14 mm × 14 mm)
User Interfaces
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
Parallel
Serial (SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible,
I
DB10/(SCLK/SCL)
2
WR/(DCEN/AD1)
DB11/(DIN/SDA)
C-compatible
CS/(SYNC/AD0)
featuring data readback)
DB9/(SPI/I
MON_IN1
MON_IN2
MON_IN3
MON_IN4
SER/PAR
FIFO EN
RESET
REG 0
REG 1
BUSY
SDO
CLR
DB8
DB0
2
PD
A4
A0
C)
V
OUT
INTERFACE
POWER-ON
DV
CONTROL
MON_OUT
RESET
LOGIC
0………V
36-TO-1
DD
MUX
AD5383
(×3)
OUT
CONTROL
MACHINE
31
STATE
LOGIC
DGND (×3)
FIFO
+
+
12
12
12
12
AV
FUNCTIONAL BLOCK DIAGRAM
DD
INPUT
REG 0
INPUT
REG 1
INPUT
REG 6
INPUT
REG 7
(×4)
12
12
12
12
12
12
12
12
12
12
12
12
m REG 0
m REG 1
m REG 6
m REG 7
AGND (×4)
c REG 0
c REG 1
c REG 6
c REG 7
×4
Figure 1.
32-Channel, 3 V/5 V, Single-Supply,
DAC GND (×4)
INTEGRATED FUNCTIONS
Channel monitor
Simultaneous output update via LDAC
Clear function to user-programmable code
Amplifier boost mode to optimize slew rate
User programmable offset and gain adjust
Toggle mode enables square wave generation
Thermal monitor
APPLICATIONS
Variable optical attenuators (VOA)
Level setting (ATE)
Optical microelectro-mechanical systems (MEMS)
Control systems
Instrumentation
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113© 2004–2010 Analog Devices, Inc. All rights reserved.
12
12
12
12
12-Bit, Voltage Output DAC
REG 0
REG 1
REG 6
REG 7
LDAC
DAC
DAC
DAC
DAC
REFGND
12
12
12
12
REFERENCE
1.25V/2.5V
DAC 0
DAC 1
DAC 6
DAC 7
REFOUT/REFIN
R
R
R
R
SIGNAL GND (×4)
R
R
R
R
www.analog.com
AD5383
V
V
V
V
V
V
V
V
V
V
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
0
1
2
3
4
5
6
7
8
31

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AD5383BST-3 Summary of contents

Page 1

FEATURES Guaranteed monotonic INL error: ±1 LSB max On-chip 1.25 V/2 ppm/°C reference Temperature range: –40°C to +85°C Rail-to-rail output amplifier Power-down mode Package type: 100-lead LQFP (14 mm × 14 mm) User Interfaces Parallel Serial (SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible, featuring ...

Page 2

AD5383 TABLE OF CONTENTS General Description ......................................................................... 3 Specifications ..................................................................................... 4 AD5383-5 Specifications ............................................................. 4 AD5383-3 Specifications ............................................................. 6 AC Characteristics ........................................................................ 7 Timing Characteristics ..................................................................... 8 Serial Interface Timing ................................................................ Serial Interface Timing ........................................................ 10 ...

Page 3

GENERAL DESCRIPTION The AD5383 is a complete, single-supply, 32-channel, 12-bit DAC available in a 100-lead LQFP package. All 32 channels have an on-chip output amplifier with rail-to-rail operation. The AD5383 includes a programmable internal 1.25 V/2 ppm/°C reference; ...

Page 4

AD5383 SPECIFICATIONS AD5383-5 SPECIFICATIONS 5.5 V, AGND = DGND = 0 V; external REFIN = 2.5 V; all specifications otherwise noted. Table 3. Parameter ACCURACY ...

Page 5

Parameter LOGIC OUTPUTS ( BUSY , SDO Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage OH High Impedance Leakage Current High Impedance Output Capacitance ...

Page 6

AD5383 AD5383-3 SPECIFICATIONS 5.5 V, AGND = DGND = 0 V; external REFIN = 1.25 V; all specifications otherwise noted. Table 4. Parameter ACCURACY Resolution ...

Page 7

Parameter 3 LOGIC OUTPUTS (BUSY, SDO Output Low Voltage Output High Voltage OH High Impedance Leakage Current High Impedance Output Capacitance 3 LOGIC OUTPUT (SDA Output Low Voltage OL Three-State Leakage Current Three-State ...

Page 8

AD5383 TIMING CHARACTERISTICS SERIAL INTERFACE TIMING 3.6 V; AGND = DGND = 0 V; all specifications noted. Table 6. ...

Page 9

SCLK SYNC DIN DB23 BUSY 1 LDAC 1 V OUT 2 LDAC 2 V OUT t 18 CLR V OUT 1 LDAC ACTIVE DURING BUSY 2 LDAC ACTIVE ...

Page 10

AD5383 SERIAL INTERFACE TIMING 3.6 V; AGND = DGND = 0 V; all specifications noted. Table ...

Page 11

PARALLEL INTERFACE TIMING 3.6 V; AGND = DGND = 0 V; all specifications noted. Table ...

Page 12

AD5383 REG0, REG1, A4..A0 DB11..DB0 BUSY LDAC V OUT LDAC V OUT CLR ...

Page 13

ABSOLUTE MAXIMUM RATINGS 25°C, unless otherwise noted . A Table 9. Parameter Rating AV to AGND –0 DGND –0 Digital Inputs to DGND –0.3 V ...

Page 14

AD5383 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS FIFO EN 1 CLR OUT OUT OUT OUT SIGNAL_GND4 7 DAC_GND4 8 AGND4 ...

Page 15

Mnemonic Function MON_OUT MON_OUT Monitor Output Pin. When the monitor function is enabled, this output acts as the output of a 36-to-1 channel multiplexer that can be programmed to multiplex one of Channels 0 to 31or any of the monitor ...

Page 16

AD5383 Mnemonic Function PD Power Down (Level Sensitive, Active High used to place the device in low power mode where the device consumes 2 μA analog supply current and 20 μA digital supply current. In power-down mode, all ...

Page 17

TERMINOLOGY Relative Accuracy Relative accuracy, or endpoint linearity measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function measured after adjusting for zero-scale error and full-scale error, and ...

Page 18

AD5383 TYPICAL PERFORMANCE CHARACTERISTICS 1.00 0.75 0.50 0.25 0 –0.25 –0.50 –0.75 –1.00 0 512 1024 1536 2048 2560 INPUT CODE Figure 9. Typical AD5383-5 INL Plot 2.539 2.538 V = 2.5V REF ...

Page 19

AI (mA) DD Figure 15. AI Histogram 0.4 0.5 0.6 0.7 0.8 DI (mA) DD Figure 16. DI Histogram DD WR BUSY AV ...

Page 20

AD5383 6 FULL-SCALE 5 AV 3/4 SCALE 4 MIDSCALE 3 2 1/4 SCALE 1 ZERO-SCALE 0 –1 –40 –20 –10 –5 – CURRENT (mA) Figure 21. AD5383-5 Output Amplifier Source and Sink Capability 0.20 0.15 0.10 ERROR AT ...

Page 21

FUNCTIONAL DESCRIPTION DAC ARCHITECTURE—GENERAL The AD5383 is a complete, single-supply, 32-channel voltage output DAC that offers 12-bit resolution. The part is available in a 100-lead LQFP package and features both a parallel and a serial interface. This product includes an ...

Page 22

AD5383 ON-CHIP SPECIAL FUNCTION REGISTERS (SFR) The AD5383 contains a number of special function registers (SFRs), as outlined in Table 15. SFRs are addressed with REG1 = REG0 = 0 and are decoded using Address Bit A4 to Address Bit ...

Page 23

Table 16. Control Register Contents MSB CR11 CR10 CR9 CR8 Control Register Write/Read REG1 = REG0 = 01100 status determines if the operation is a write ( read ...

Page 24

AD5383 Table 18. Channel Monitor Decoding REG1 REG0 ...

Page 25

HARDWARE FUNCTIONS RESET FUNCTION Bringing the RESET line low resets the contents of all internal registers to their power-on reset state. RESET is a negative edge- sensitive input. The default corresponds full scale and ...

Page 26

AD5383 INTERFACES The AD5383 contains both parallel and serial interfaces. Furthermore, the serial interface can be programmed C-compatible. The SER/ PAR SPI-, DSP-, MICROWIRE pin selects parallel and serial interface modes. In serial mode, the ...

Page 27

Daisy-Chain Mode For systems that contain several devices, the SDO pin may be used to daisy-chain several devices together. This daisy-chain mode can be useful in system diagnostics and in reducing the number of serial interface lines. By connecting the ...

Page 28

AD5383 SERIAL INTERFACE 2 The AD5383 features an I C-compatible, 2-wire interface consisting of a serial data line (SDA) and a serial clock line (SCL). SDA and SCL facilitate communication between the AD5383 and the master at ...

Page 29

SCL SDA START COND BY MASTER ADDRESS BYTE SCL REG1 REG0 MSB SDA MOST SIGNIFICANT BYTE SCL SDA START COND BY MASTER ADDRESS BYTE SCL SDA REG1 REG0 MSB MOST ...

Page 30

AD5383 2-Byte Mode Following initialization of 2-byte mode, the user can sequentially update channels. The device address byte is only required once, and the address pointer is configured for auto- increment or burst mode. The user must begin with an ...

Page 31

MICROPROCESSOR INTERFACING Parallel Interface The AD5383 can be interfaced to a variety of 16-bit microcon- trollers or DSP processors. Figure 35 shows the AD5383 family interfaced to a generic 16-bit microcontroller/DSP processor. The lower address lines from the processor are ...

Page 32

AD5383 AD5383 to PIC16C6x/7x The PIC16C6x/7x synchronous serial port (SSP) is configured as an SPI master with the clock polarity bit = 0. This is done by writing to the synchronous serial port control register (SSPCON). See the PIC16/17 Microcontroller ...

Page 33

APPLICATION INFORMATION POWER SUPPLY DECOUPLING In any circuit where accuracy is important, careful considera- tion of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5383 is mounted should ...

Page 34

AD5383 CHANNEL MONITOR FUNCTION The AD5383 contains a channel monitor function that consists of a multiplexer addressed via the interface, allowing any chan- nel output to be routed to this pin for monitoring using an external ADC. The channel monitor ...

Page 35

INPUT INPUT DATA REGISTER A/B DWDM IN FIBRE AWG OPTICAL ATTENUATORS Based on its high channel count, high resolution, monotonic behavior, and high level of integration, the AD5383 is ideally targeted at optical attenuation applications used in dynamic gain equalizers, ...

Page 36

AD5383 UTILIZING THE FIFO The AD5383 FIFO mode optimizes total system update rates in applications where a large number of channels need to be updated. FIFO mode is only available when parallel interface mode is selected. The FIFO EN pin ...

Page 37

... OUTLINE DIMENSIONS 1.45 1.40 1.35 0.15 SEATING 0.05 PLANE VIEW A ROTATED 90° CCW ORDERING GUIDE 1 Model Resolution AD5383BSTZ-3 12 Bits AD5383BSTZ-5 12 Bits RoHS Compliant Part. 16.20 16.00 SQ 1.60 MAX 15.80 0.75 100 1 0.60 0.45 PIN 1 (PINS DOWN) 0.20 0.09 7° 3.5° ...

Page 38

AD5383 NOTES Rev Page ...

Page 39

NOTES Rev Page AD5383 ...

Page 40

AD5383 NOTES refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2004–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03734–0–4/10(B) Rev ...

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