DAC1232LCJ National Semiconductor, DAC1232LCJ Datasheet - Page 3

IC DAC 12BIT DBL BUFFERED 20-DIP

DAC1232LCJ

Manufacturer Part Number
DAC1232LCJ
Description
IC DAC 12BIT DBL BUFFERED 20-DIP
Manufacturer
National Semiconductor
Series
MICRO-DAC™r
Datasheet

Specifications of DAC1232LCJ

Settling Time
1µs
Number Of Bits
12
Data Interface
Parallel
Number Of Converters
1
Voltage Supply Source
Single Supply
Power Dissipation (max)
500mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Through Hole
Package / Case
*
Case
DIP-20L
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
*DAC1232LCJ

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AC CHARACTERISTICS
Symbol
t
t
t
t
t
t
Electrical Characteristics
V
Note 13) all other limits T
Note 1 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions
Note 2 All voltages are measured with respect to GND unless otherwise specified
Note 3 This 500 mW specification applies for all packages The low intrinsic power dissipation of this part (and the fact that there is no way to significantly modify
the power dissipation) removes concern for heat sinking
Note 4 Both I
example if V
Note 5 Tested and guaranteed to National’s AOQL (Average Outgoing Quality Level)
Note 6 Design limits are guaranteed but not 100% tested These limits are not used to calculate outgoing quality levels Guaranteed for V
and V
Note 7 The unit FSR stands for full-scale range Linearity Error and Power Supply Rejection specs are based on this unit to eliminate dependence on a particular
V
performing a zero and full-scale adjustment the plot of the 4096 analog voltage outputs will each be within 0 012%
zero and full-scale The unit ppm of FSR(parts per million of full-scale range) and ppm of FS(parts per million of full-scale) are used for convenience to define specs
of very small percentage values typical of higher accuracy converters In this instance 1 ppm of FSR
output voltage quantity For example the gain error tempco spec of
b
Note 8 This spec implies that all parts are guaranteed to operate with a write pulse or transfer pulse width (t
100 ns The entire write pulse must occur within the valid data interval for the specified t
Note 9 To achieve this low feedthrough in the D package the user must ground the metal lid If the lid is left floating the feedthrough is typically 6 mV
Note 10 Typicals are at 25 C and represent the most likely parametric norm
Note 11 A 10 nA leakage current with R
Note 12 Human body model 100 pF discharged through a 1 5 k
Note 13 Tested limit for
Connection Diagrams
s
W
DS
DH
CS
CH
REF
REF
40 C to
REF
value to indicate the true performance of the part The Linearity Error specification of the DAC1208 is 0 012% of FSR(max) This guarantees that after
e
e b
a
10 000 V
85 C of
REF
OUT1
10V to
Current Setting Time
Write and XFER
Pulse Width Min
Data Setup Time Min
Data Hold Time Min
Control Setup Time Min
Control Hold Time Min
e
10V then a 1 mV offset V
and I
g
DC
a
(6)(V
OUT2
Parameter
10V
b
1 suffix parts applies only at 25 C
V
REF
CC
must go to ground or the virtual ground of an operational amplifier The linearity error is degraded by approximately V
Dual-In-Line Package
10
A
e
6
e
)(125 C) or
11 4 V
T
Fb
J
e
e
OS
20k and V
DC
25 C
g
on I
to 15 75 V
0 75 (10
OUT1
V
V
V
V
V
V
(Continued)
IL
IL
IL
IL
IL
IL
REF
b
e
e
e
e
e
e
or I
Conditions
e
3
) V
0V V
0V V
0V V
0V V
0V V
0V V
10V corresponds to a zero error of (10
OUT2
DC
REF
unless otherwise noted Boldface limits apply from T
g
resistor
will introduce an additional 0 01% linearity error
which is
IH
IH
IH
IH
IH
IH
6 ppm of FS C represents a worst-case full-scale gain error change with temperature from
e
e
e
e
e
e
5V
5V
5V
5V
5V
5V
g
3
0 075% of V
Note
See
8
W
t
REF
DS
Dual-In-Line Package
t
DH
See Ordering Information
(Note 10)
and t
c
e
Typ
10
1 0
50
70
30
60
0
V
S
b
REF
W
9 c
to apply
) of 320 ns A typical part will operate with t
20
10
c
6
c
10
is the conversion factor to provide an actual
V
3
REF
(Note 5)
)
Tested
c
Limit
100% 10V or 0 002% of FS
of a straight line which passes through
(Note 6)
Design
MIN
CC
Limit
320
320
320
TL H 5690 – 2
320
320
320
90
90
10
e
to T
11 4V to 15 75V
OS
MAX
d
V
W
REF
of only
Units
(see
ns
For
s

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