ATF1502ASV-15JU44 Atmel, ATF1502ASV-15JU44 Datasheet
ATF1502ASV-15JU44
Specifications of ATF1502ASV-15JU44
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ATF1502ASV-15JU44 Summary of contents
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... Fast Registered Input from Product Term • Programmable “Pin-keeper” Option • V Power-up Reset Option CC • Pull-up Option on JTAG Pins TMS and TDI • Advanced Power Management Features – Individual Macrocell Power Option High- performance EEPROM CPLD ATF1502ASV 1615J–PLD–01/06 ...
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... The ATF1502ASV’s enhanced routing switch matrices increase usable gate count and the odds of successful pin-locked design modifications. The ATF1502ASV has bi-directional I/O pins and four dedicated input pins, depending on the type of device package selected. Each dedicated pin can also serve as a global control signal, register clock, register reset or output enable ...
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... I/O pin also feeds into the global bus. The switch matrix in each logic block then selects 40 individual signals from the global bus. Each macrocell also generates a foldback logic term that goes to a regional bus. Cascade logic between macrocells in the ATF1502ASV allows fast, effi- cient generation of complex logic functions. The ATF1502ASV contains four such logic chains, each capable of creating sum term logic with a fan- product terms ...
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... OR/XOR/CASCADE Logic The ATF1502ASV’s logic structure is designed to efficiently support all types of logic. Within a single macrocell, all the product terms can be routed to the OR gate, creating a 5-input AND/OR sum term. With the addition of the CASIN from neighboring macrocells, this can be expanded to as many as 40 product terms with little additional delay. The macrocell’ ...
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... Programmable Pin-keeper Option for Inputs and I/Os The ATF1502ASV offers the option of programming all input and I/O pins so that pin-keeper cir- cuits can be utilized. When any pin is driven high or low and then subsequently left floating, it will stay at that previous high or low level. This circuitry prevents unused input and I/O lines from 1615J– ...
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... OFF to ON) for any or all macrocells. The ATF1502ASV also has an optional power-down mode. In this mode, current drops to below 15 mA. When the power-down option is selected, either PD1 or PD2 pins (or both) can be used to power down the part ...
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... The ATF1502ASV macrocell also has an option whereby the power can be reduced on a per- macrocell basis. By enabling this power-down option, macrocells that are not used in an applica- tion can be turned down, thereby reducing the overall power consumption of the device. ...
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... JTAG control pins are available as I/O pins. 7.1 JTAG Boundary-scan Cell (BSC) Testing The ATF1502ASV contains I/O pins and four input pins, depending on the device type and package type selected. Each input pin and I/O pin has its own boundary-scan cell (BSC) in ATF1502ASV 8 For more information refer to the “ ...
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... BSC Configuration for Input and I/O Pins (Except JTAG TAP Pins) Dedicated Input To Internal Logic TDI (From Next Register) The ATF1502ASV has a pull-up option on TMS and TDI pins. This feature is selected as a design option. ATF1502ASV Capture Registers CLOCK SHIFT TDO ...
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... Figure 7-2. 8. Design Software Support ATF1502ASV designs are supported by several third-party tools. Automated fitters allow logic synthesis using a variety of high-level description languages and formats. ATF1502ASV 10 BSC Configuration for Macrocells TDO TDI CLOCK TDO OEJ OUTJ Capture DR TDI Shift BSC for I/O Pins and Macrocells ...
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... Max Units ATF1502ASV Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied ...
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... Output Low Voltage (CMOS) Output High Voltage (TTL Output High Voltage (CMOS) Notes: 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec refers to the current in the reduced-power mode when macrocell reduced-power is turned on. CC3 ATF1502ASV 12 Condition GND ...
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... GLOB Delay t IN Logic Array Switch Delay t Matrix LAD t UIM Register Control Delay t LAC Foldback Term Delay t SEXP 1.5 ns typical 703Ω 8060Ω ATF1502ASV Register Cascade Logic Delay Delay Output Delay PEXP OD1 t PRE t OD2 t CLR t OD3 COMB t ZX1 t ...
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... Internal Output Enable Delay IOE Output Buffer and Pad Delay t (Slow slew rate = OFF; OD1 V = 3.3V pF Output Buffer Enable Delay t (Slow slew rate = OFF; ZX1 V = 5.0V pF) CCIO L Output Buffer Enable Delay t (Slow slew rate = OFF; ZX2 V = 3.3V pF) CCIO L ATF1502ASV 14 -15 -20 Min Max Min Max 1 ...
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... Register Enable Time EN t Global Control Delay GLOB t Register Preset Time PRE t Register Clear Time CLR t Switch Matrix Delay UIM t Reduced-power Adder RPA Notes: 1. See ordering information for valid part numbers. 1615J–PLD–01/ pF) L (2) ATF1502ASV -15 -20 Min Max Min Max ...
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... Power-down Mode The ATF1502ASV includes an optional pin-controlled power-down feature. When this mode is enabled, the PD pin acts as the power-down pin. When the PD pin is high, the device supply cur- rent is reduced to less than 3 mA. During power-down, all output data and internal logic states are latched and held ...
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... ATF1502ASV Dedicated Pinouts Figure 15-1. ATF1502ASV Dedicated Pinouts Dedicated Pin INPUT/OE2/GCLK2 INPUT/GCLR INPUT/OE1 INPUT/GCLK1 I/O / GCLK3 I (1,2) I/O / TDI (JTAG) I/O / TMS (JTAG) I/O / TCK (JTAG) I/O / TDO (JTAG) GND V CCI # of Signal Pins # User I/O Pins OE (1, 2) GCLR GCLK ( (1, 2) TDI, TMS, TCK, TDO ...
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... Figure 15-2. ATF1502ASV I/O Pinouts 4/TDI 7/PD1 9/TMS 20/TDO 25/TCK 31/PD2 ATF1502ASV 18 MC PLC 44-lead PLCC 44-lead TQFP 1615J–PLD–01/06 ...
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... FREQUENCY (MHz) 1615J–PLD–01/06 3.4 3.5 3.6 = 25° 3.4 3.5 3.6 = 25°C) A REDUCED POWER 60.00 80.00 100.00 ATF1502ASV OUTPUT SOURCE CURRENT VS. SUPPLY VOLTAGE (V = 2.4V 25° -10 -12 -14 -16 2.75 3.00 3.25 3.50 SUPPLY VOLTAGE (V) SUPPLY CURRENT VS. SUPPLY VOLTAGE ASVL (LOW-POWER) VERSION (T = 25° ...
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... SUPPLY VOLTAGE (V) INPUT CLAMP CURRENT VS. INPUT VOLTAGE (V = 3.3V 25° -20 -40 -60 -80 -100 -1 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 INPUT VOLTAGE (V) ATF1502ASV 20 100 2.5 3.0 3.5 4 -10 3.75 4.00 0 -0.3 -0.2 -0.1 0 OUTPUT SINK CURRENT VS. OUTPUT VOLTAGE ( ...
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... Notes: 1. The last-time buy date was September 30, 2005 for shaded parts 2004, Atmel briefly offered lead-free ATF1502ASV-15JJ44. This part is now discontinued and replaced by ATF1502ASV-15JU44, which is both lead- and Halide-free. 16.2 Green Package Options (Pb/Halide-free/RoHS Compliant CO1 MAX (ns) ...
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... This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. 2325 Orchard Parkway San Jose, CA 95131 R ATF1502ASV TITLE 44A, 44-lead Body Size, 1 ...
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... Lead coplanarity is 0.004" (0.102 mm) maximum. 2325 Orchard Parkway San Jose, CA 95131 R 1615J–PLD–01/06 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER TITLE 44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC) ATF1502ASV 0.318(0.0125) 0.191(0.0075) D2/ COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX A 4.191 – ...
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... Revision History Version Number/Release Date Comments Revision I – June 2005 Added Green package options Revision J – January 2006 Updated ATF1502ASV-15JC44 to last-time buy status ATF1502ASV 24 1615J–PLD–01/06 ...
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