ATF1504ASL-20AC44 Atmel, ATF1504ASL-20AC44 Datasheet

IC CPLD 64 MACROCELL LP 44TQFP

ATF1504ASL-20AC44

Manufacturer Part Number
ATF1504ASL-20AC44
Description
IC CPLD 64 MACROCELL LP 44TQFP
Manufacturer
Atmel
Series
ATF1504AS(L)r
Datasheet

Specifications of ATF1504ASL-20AC44

Programmable Type
In System Programmable (min 10K program/erase cycles)
Delay Time Tpd(1) Max
20.0ns
Voltage Supply - Internal
4.75 V ~ 5.25 V
Number Of Macrocells
64
Number Of I /o
32
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
44-TQFP, 44-VQFP
Voltage
5V
Memory Type
EEPROM
For Use With
ATF15XX-DK3 - KIT DEV FOR ATF15XX CPLD'S
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Number Of Logic Elements/cells
-
Other names
ATF1504ASL20AC44

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATF1504ASL-20AC44
Manufacturer:
Atmel
Quantity:
10 000
Features
Enhanced Features
High-density, High-performance, Electrically-erasable Complex Programmable
Logic Device
In-System Programmability (ISP) via JTAG
Flexible Logic Macrocell
Advanced Power Management Features
Available in Commercial and Industrial Temperature Ranges
Available in 44-, 68-, and 84-lead PLCC; 44- and 100-lead TQFP; and 100-lead PQFP
Advanced EE Technology
JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported
PCI-compliant
3.3V or 5.0V I/O Pins
Security Fuse Feature
Green (Pb/Halide-fee/RoHS Compliant) Package Options
Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)
Output Enable Product Terms
Transparent – Latch Mode
Combinatorial Output with Registered Feedback within Any Macrocell
Three Global Clock Pins
ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O
Fast Registered Input from Product Term
Programmable “Pin-keeper” Option
V
Pull-up Option on JTAG Pins TMS and TDI
Advanced Power Management Features
CC
– 64 Macrocells
– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell
– 44, 68, 84, 100 Pins
– 7.5 ns Maximum Pin-to-pin Delay
– Registered Operation up to 125 MHz
– Enhanced Routing Resources
– D/T/Latch Configurable Flip-flops
– Global and Individual Register Control Signals
– Global and Individual Output Enable
– Programmable Output Slew Rate
– Programmable Output Open Collector Option
– Maximum Logic Utilization by Burying a Register with a COM Output
– Automatic µA Standby for “L” Version
– Pin-controlled 1 mA Standby Mode
– Programmable Pin-keeper Circuits on Inputs and I/Os
– Reduced-power Feature per Macrocell
– 100% Tested
– Completely Reprogrammable
– 10,000 Program/Erase Cycles
– 20-year Data Retention
– 2000V ESD Protection
– 200 mA Latch-up Immunity
– Edge-controlled Power-down “L”
– Individual Macrocell Power Option
– Disable ITD on Global Clocks, Inputs and I/O
Power-up Reset Option
High-
performance
Complex
Programmable
Logic Device
ATF1504AS
ATF1504ASL
Rev. 0950O–PLD–7/05
1

Related parts for ATF1504ASL-20AC44

ATF1504ASL-20AC44 Summary of contents

Page 1

... Pull-up Option on JTAG Pins TMS and TDI • Advanced Power Management Features – Edge-controlled Power-down “L” – Individual Macrocell Power Option – Disable ITD on Global Clocks, Inputs and I/O High- performance Complex Programmable Logic Device ATF1504AS ATF1504ASL Rev. 0950O–PLD–7/05 1 ...

Page 2

TQFP Top View I/O/TDI 1 I/O 2 I/O 3 GND 4 PD1/I/O 5 I/O 6 TMS/I/O 7 I/O 8 VCC 9 I/O 10 I/O 11 68-lead PLCC Top View I/O 10 VCCIO 11 I/O/TD1 12 I/O 13 I/O 14 ...

Page 3

PQFP Top View I/O 3 I/O 4 VCCIO 5 I/O/TDI I I/O 10 I/O 11 I/O 12 GND 13 I/O/PD1 14 I/O 15 I/O 16 I/O/TMS 17 I/O 18 ...

Page 4

... The ATF1504AS is a high-performance, high-density complex programmable logic device (CPLD) that utilizes Atmel’s proven electrically-erasable memory technology. With 64 logic macrocells and inputs, it easily integrates logic from several TTL, SSI, MSI, LSI and classic PLDs. The ATF1504AS’s enhanced routing switch matrices increase usable gate count and the odds of successful pin-locked design modifications ...

Page 5

Block Diagram I/O (MC64)/GCLK3 0950O–PLD–7/05 Unused product terms are automatically disabled by the compiler to decrease power consumption. A security fuse, when programmed, protects the contents of the ATF1504AS. Two bytes (16 bits) of User Signature are accessible to the ...

Page 6

Product Terms and Select Mux OR/XOR/CASCADE Logic Flip-flop Output Select and Enable Global Bus/Switch Matrix ATF1504AS(L) 6 Each ATF1504AS macrocell has five product terms. Each product term receives as its possible inputs all signals from both the global bus and ...

Page 7

Foldback Bus Figure 1. ATF1504AS Macrocell 0950O–PLD–7/05 Each macrocell also generates a foldback product term. This signal goes to the regional bus and is available to four macrocells. The foldback is an inverse polarity of one of the macrocell’s product ...

Page 8

Programmable Pin- keeper Option for Inputs and I/Os Input Diagram Speed/Power Management I/O Diagram ATF1504AS(L) 8 The ATF1504AS offers the option of programming all input and I/O pins so that pin- keeper circuits can be utilized. When any pin is ...

Page 9

... The ATF1504AS has two options for the hysteresis about the reset level, V and Large. During the fitting process users may configure the device with the Power-up Reset hysteresis set to Large or Small. Atmel POF2JED users may select the Large option by including the flag “-power_reset” on the command line after “filename.POF”. ...

Page 10

... This capability eliminates package handling normally required for programming and facilitates rapid design iterations and field changes. Atmel provides ISP hardware and software to allow programming of the ATF1504AS via the PC. ISP is performed by using either a download cable or a comparable board tester or a simple microprocessor interface. ...

Page 11

DC and AC Operating Conditions Operating Temperature (Ambient (5V) Power Supply CCINT CCIO V (3.3V) Power Supply CCIO DC Characteristics Symbol Parameter Input or I/O Low I IL Leakage Current Input or I/O High I IH Leakage ...

Page 12

Absolute Maximum Ratings* Temperature Under Bias.................................. -40°C to +85°C Storage Temperature ..................................... -65°C to +150°C Voltage on Any Pin with Respect to Ground .........................................-2.0V to +7.0V Voltage on Input Pins with Respect to Ground During Programming.....................................-2.0V to +14.0V Programming Voltage ...

Page 13

AC Characteristics (Continued) Symbol Parameter f Maximum Clock Frequency MAX t Input Pad and Buffer Delay IN t I/O Input Pad and Buffer Delay IO t Fast Input Delay FIN t Foldback Term Delay SEXP t Cascade Logic Delay PEXP ...

Page 14

AC Characteristics (Continued) Symbol Parameter Output Buffer Enable Delay t (Slow slew rate = OFF; ZX1 V = 5.0V pF) CCIO L Output Buffer Enable Delay t (Slow slew rate = OFF; ZX2 V = 3.3V; C ...

Page 15

Output AC Test Loads Note: *Numbers in parenthesis refer to 3.0V operating conditions (preliminary). Power-down Mode Power Down AC Characteristics Symbol Parameter t Valid I, I/O before PD High IVDH (2) t Valid OE before PD High GVDH (2) t ...

Page 16

JTAG-BST/ISP Overview JTAG Boundary-scan Cell (BSC) Testing BSC Configuration for Input and I/O Pins (Except JTAG TAP Pins) Note: The ATF1504AS has pull-up option on TMS and TDI pins. This feature is selected as a design option. ATF1504AS(L) 16 The ...

Page 17

BSC Configuration for Macrocell 0950O–PLD–7/05 Pin BSC 0 Pin 1 TDI Shift TDO OEJ OUTJ Capture Update DR DR TDI Clock Shift Macrocell BSC ATF1504AS(L) TDO D Q ...

Page 18

PCI Compliance PCI Voltage-to-current Curves for +5V Signaling in Pull-up Mode PCI Voltage-to-current Curves for +5V Signaling in Pull-down Mode ATF1504AS(L) 18 The ATF1504AS also supports the growing need in the industry to support the new Peripheral Component Interconnect (PCI) ...

Page 19

PCI DC Characteristics Symbol Parameter V Supply Voltage CC V Input High Voltage IH V Input Low Voltage IL I Input High Leakage Current IH I Input Low Leakage Current IL V Output High Voltage OH V Output Low Voltage ...

Page 20

ATF1504AS Dedicated Pinouts 44-lead Dedicated Pin TQFP INPUT/OE2/GCLK2 40 INPUT/GCLR 39 INPUT/OE1 38 INPUT/GCLK1 37 I/O /GCLK3 35 I/O/PD (1, I/O/TDI (JTAG) 1 I/O/TMS (JTAG) 7 I/O/TCK (JTAG) 26 I/O/TDO (JTAG) 32 GND 4, 16, 24 ...

Page 21

ATF1504AS I/O Pinouts 44- 44- 68- lead lead lead MC PLC PLCC TQFP PLCC – – – PD1 ...

Page 22

SUPPLY CURRENT VS. SUPPLY VOLTAGE (T = 25° 125 100 STANDARD 4.50 4.75 5.00 V (V) CC SUPPLY CURRENT VS. SUPPLY VOLTAGE LOW-POWER ("L") VERSION (T = 25° ...

Page 23

OUTPUT SINK CURRENT VS. SUPPLY VOLTAGE (VOL = 0.5V 4.50 4.75 5.00 SUPPLY VOLTAGE (V) NORMALIZED TPD VS. SUPPLY VOLTAGE (T 1.20 1.10 1.00 0.90 0.80 4.5 4.8 ...

Page 24

NORMALIZED TCO VS.TEMPERATURE (V CC 1.2 1.1 1.0 0.9 0.8 -40.0 0.0 TEMPERATURE (C) NORMALIZED TSU VS. TEMPERATURE (V CC 1.2 1.1 1.0 0.9 0.8 -40.0 0.0 TEMPERATURE (C) ATF1504AS( 5.0V) 25.0 75.0 = 5.0V) 25.0 75.0 0950O–PLD–7/05 ...

Page 25

Ordering Information ATF1504AS Standard Package Options CO1 MAX (ns) (ns) (MHz) 7.5 4.5 166 125 10 5 125 15 8 100 15 8 100 Notes: 1. The last time buy date is Sept. 30, ...

Page 26

ATF1504AS Green Package Options (Pb/Halide-free/RoHS Compliant CO1 MAX (ns) (ns) (MHz) 7.5 4.5 166 125 44A 44-lead, Thin Plastic Gull Wing Quad Flatpack (TQFP) 44J 44-lead, Plastic J-leaded Chip Carrier (PLCC) 68J 68-lead, Plastic ...

Page 27

... The last time buy date is Sept. 30, 2005 for shaded parts. Using “C” Product for Industrial To use commercial product for Industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device (7 ns “C” “I”) and de-rate power by 30%. ATF1504ASL Green Package Options (Pb/Halide-free/RoHS Compliant ...

Page 28

Packaging Information 44A – TQFP PIN 1 PIN 1 IDENTIFIER e C 0˚~7˚ L Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm ...

Page 29

PLCC 1.14(0.045) X 45˚ 0.51(0.020)MAX 45˚ MAX (3X) Notes: 1. This package conforms to JEDEC reference MS-018, Variation AC. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. ...

Page 30

PLCC 1.14(0.045) X 45˚ 0.51(0.020)MAX 45˚ MAX (3X) Notes: 1. This package conforms to JEDEC reference MS-018, Variation AE. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. ...

Page 31

PLCC 1.14(0.045) X 45˚ 0.51(0.020)MAX 45˚ MAX (3X) Notes: 1. This package conforms to JEDEC reference MS-018, Variation AF. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. ...

Page 32

PQFP PIN 1 ID PIN 0º~7º C 2325 Orchard Parkway San Jose, CA 95131 R ATF1504AS( TITLE 100Q1, 100-lead Body, 3.2 mm Footprint, ...

Page 33

TQFP PIN 0˚~7˚ L Notes: 1. This package conforms to JEDEC reference MS-026, Variation AED. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and ...

Page 34

Revision History ATF1504AS(L) 34 Revision Comments Green package options added. 0950O 0950O–PLD–7/05 ...

Page 35

... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...

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