ATF1504ASV-15AU44 Atmel, ATF1504ASV-15AU44 Datasheet
ATF1504ASV-15AU44
Specifications of ATF1504ASV-15AU44
Available stocks
Related parts for ATF1504ASV-15AU44
ATF1504ASV-15AU44 Summary of contents
Page 1
... Pull-up Option on JTAG Pins TMS and TDI • Advanced Power Management Features – Edge-controlled Power-down “L” – Individual Macrocell Power Option – Disable ITD on Global Clocks, Inputs and I/O Low-voltage, Complex Programmable Logic Device ATF1504ASV ATF1504ASVL Rev. 1409J–PLD–6/05 1 ...
Page 2
... PLCC Top View I/O 10 VCCIO 11 I/O/TD1 12 I/O 13 I/O 14 I/O 15 GND 16 I/O/PD1 17 I/O 18 I/O/TMS 19 I/O 20 VCCIO 21 I/O 22 I/O 23 I/O 24 I/O 25 GND 26 ATF1504ASV(L) 2 TDI/I/O 33 I/O 32 I/O/TDO 31 I/O PD1/I/O 30 I/O 29 VCC I/O/TMS 28 I/O 27 I/O 26 I/O/TCK 25 I/O 24 GND 23 I/O I I/O VCCIO 13 59 I/O I/O/TDI ...
Page 3
... I/O I/O/TMS 15 66 I/O I I/O I I/O/TCK VCCIO 18 63 I/O I I/O I GND I I I I/O 53 VCCIO ATF1504ASV(L) 100-lead TQFP Top View 75 I/O 74 GND 73 I/O/TDO I I/O 68 I/O 67 I/O 66 VCCIO 65 I/O 64 I/O 63 I/O 62 I/O/TCK 61 I/O 60 I/O 59 GND 58 I/O 57 I I/O 51 VCCIO 3 ...
Page 4
... The ATF1504ASV(L) has bi-directional I/O pins and four dedicated input pins, depending on the type of device package selected. Each dedicated pin can also serve as a global control signal, register clock, register reset or output enable. Each of these control signals can be selected for use individually within each macrocell ...
Page 5
... Unused product terms are automatically disabled by the compiler to decrease power consumption. A security fuse, when programmed, protects the contents of the ATF1504ASV(L). Two bytes (16 bits) of User Signature are accessible to the user for purposes such as storing project name, part number, revision or date. The User Signa- ture is accessible regardless of the state of the security fuse ...
Page 6
... Foldback Bus ATF1504ASV(L) 6 The ATF1504ASV(L)’s logic structure is designed to efficiently support all types of logic. Within a single macrocell, all the product terms can be routed to the OR gate, creating a 5-input AND/OR sum term. With the addition of the CASIN from neighboring macrocells, this can be expanded to as many as 40 product terms with little additional delay. ...
Page 7
... Programmable Pin-keeper Option for Inputs and I/Os The ATF1504ASV(L) offers the option of programming all input and I/O pins so that pin keeper circuits can be utilized. When any pin is driven high or low and then subsequently left floating, it will stay at that previous high- or low-level. This cir- cuitry prevents unused input and I/O lines from floating to intermediate voltage levels, which causes unnecessary power consumption and system noise ...
Page 8
... This feature allows individual macrocells to be configured for maximum power savings. This feature may be selected as a design option. All ATF1504ASV(L) also have an optional power-down mode. In this mode, current drops to below 5 mA. When the power-down option is selected, either PD1 or PD2 pins (or both) can be used to power down the part ...
Page 9
... Automated fitters allow logic synthesis using a variety of high-level description lan- guages and formats. The ATF1504ASV is designed with a power-up reset, a feature critical for state machine initialization point delayed slightly from V tialized, and the state of each output will depend on the polarity of its buffer. However, ...
Page 10
... JTAG protocol. This capability eliminates package handling normally required for pro- gramming and facilitates rapid design iterations and field changes ATF1504ASV(L) via the PC. ISP is performed by using either a download cable, a com- parable board tester or a simple microprocessor interface. To facilitate ISP programming by the Automated Test Equipment (ATE) vendors. Serial Vector Format (SVF) files can be created by Atmel provided software utilities ...
Page 11
... Min 0.1 mA Ind Min -2.0 mA CCIO Min -0.1 mA CCIO OH Max Units Conditions ATF1504ASV(L) Commercial Industrial - 3.0V - 3.6V 3.0V - 3.6V Min Typ Max - -0.3 0.8 1 0.3 CCIO 0.45 0.45 0.2 0.2 2 0.2 CCIO = 0V 1.0 MHz 1.0 MHz OUT Units µA µ ...
Page 12
... Respect to Ground .........................................-2.0V to +7.0V Voltage on Input Pins with Respect to Ground During Programming.....................................-2.0V to +14.0V Programming Voltage with Respect to Ground .......................................-2.0V to +14.0V Timing Model Input Delay t IN Switch Matrix t UIM ATF1504ASV(L) 12 *NOTICE: (1) (1) Note: 1. (1) Internal Output Enable Delay t IOE Global Control Delay t ...
Page 13
... OD2 (Slow slew rate = OFF; V Output Buffer and Pad Delay t OD3 (Slow slew rate = ON; V Output Buffer Enable Delay t ZX1 (Slow slew rate = OFF; V 1409J–PLD–6/ pF) CCIO L = 3.3V pF) CCIO 3.3V pF) CCIO L = 5.0V pF) CCIO L ATF1504ASV(L) -15 -20 Min Max Min Max 13 1 ...
Page 14
... RPA Notes: 1. See ordering information for valid part numbers. 2. The t parameter must be added to the t RPA power mode. 3. See ordering information for valid part numbers. Input Test Waveforms and Measurement Levels 1.5 ns typical R F Output AC Test Loads ATF1504ASV( 3.3V pF) CCIO L = 5.0V/3.3V pF) CCIO pF ...
Page 15
... RPA 1409J–PLD–6/05 The ATF1504ASV(L) includes an optional pin-controlled power-down feature. When this mode is enabled, the PD pin acts as the power-down pin. When the PD pin is high, the device supply current is reduced to less than 3 mA. During power down, all output data and internal logic states are latched internally and held ...
Page 16
... If JTAG (BST or ISP) is not needed, then the four JTAG control pins are avail- able as I/O pins. The ATF1504ASV(L) contains I/O pins and four input pins, depending on the device type and package type selected. Each input pin and I/O pin has its own bound- ary-scan cell (BSC) in order to support boundary-scan testing as described in detail by IEEE Standard 1149 ...
Page 17
... BSC Configuration for Macrocell 1409J–PLD–6/05 Pin BSC 0 Pin 1 TDI Shift TDO OEJ OUTJ Capture Update DR DR TDI Clock Shift Macrocell BSC ATF1504ASV(L) TDO D Q Capture DR Clock Pin 1 Mode 17 ...
Page 18
... ATF1504ASV Dedicated Pinouts 44-lead Dedicated Pin TQFP INPUT/OE2/GCLK2 40 INPUT/GCLR 39 INPUT/OE1 38 INPUT/GCLK1 37 I/O /GCLK3 35 I (1, I/O / TDI (JTAG) 1 I/O / TMS (JTAG) 7 I/O / TCK (JTAG) 26 I/O / TDO (JTAG) 32 GND 4, 16, 24 17, 29 N/C – Signal Pins 36 # User I/O Pins 32 OE (1, 2) Global OE pins GCLR ...
Page 19
... ATF1504ASV I/O Pinouts 44-lead 44-lead 68-lead MC PLC PLCC TQFP PLCC PD1 TDI 32 TMS 1409J–PLD–6/05 100- 100- 84-lead lead lead PLCC PQFP TQFP 100 100 48 TCK 56 TDO ATF1504ASV(L) 44-lead 44-lead 68-lead 84-lead PLC PLCC TQFP PLCC PLCC PD2 GCLK3 100- ...
Page 20
... FREQUENCY (MHz) SUPPLY CURRENT VS. SUPPLY VOLTAGE LOW-POWER ("L") VERSION (T = 25° 2.50 2.75 3.00 3.25 SUPPLY VOLTAGE (V) ATF1504ASV(L) 20 REDUCED POWER MODE 3.50 3.75 4.00 3.50 3.75 4.00 = 25°C) A 80.00 100.00 3.50 3.75 4.00 SUPPLY CURRENT VS. FREQUENCY LOW-POWER ("L") VERSION (T = 25° ...
Page 21
... INPUT CLAMP CURRENT VS. INPUT VOLTAGE (V = 3.3V 25° -20 -40 -60 -80 -100 -1 -0.9 -0.8 -0.7 -0.6 -0.5 INPUT VOLTAGE (V) 1409J–PLD–6/05 2.5 3 3.5 4 -0.4 -0.3 -0.2 -0.1 0 ATF1504ASV(L) INPUT CURRENT VS. INPUT VOLTAGE (V = 3.3V 25° -10 0 0.5 1 1.5 2 2.5 INPUT VOLTAGE (V) 3 3.5 21 ...
Page 22
... Ordering Information ATF1504ASV(L) Standard Package Options CO1 MAX (ns) (ns) (MHz 100 15 8 100 83.3 Note: 1. The last time buy is Sept. 30, 2005 for shaded parts. 2. The recommended migration for QC100 or JC68 packages is the AU100 or the smaller JU44 packages. 3. The recommended migration for the JC84 package is the ATF1508ASV-15JU84 Using “ ...
Page 23
... ATF1504ASV(L) Green Package Options (Pb/Halide-free/RoHS Compliant CO1 MAX (ns) (ns) (MHz 100 20 12 83.3 44A 44-lead, Thin Plastic Gull Wing Quad Flatpack (TQFP) 44J 44-lead, Plastic J-leaded Chip Carrier (PLCC) 68J 68-lead, Plastic J-leaded Chip Carrier (PLCC) 84J 84-lead, Plastic J-leaded Chip Carrier (PLCC) ...
Page 24
... This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. 2325 Orchard Parkway San Jose, CA 95131 R ATF1504ASV( TITLE 44A, 44-lead Body Size, 1 ...
Page 25
... Lead coplanarity is 0.004" (0.102 mm) maximum. 2325 Orchard Parkway San Jose, CA 95131 R 1409J–PLD–6/05 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER TITLE 44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC) ATF1504ASV(L) 0.318(0.0125) 0.191(0.0075) D2/ COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX A 4.191 – ...
Page 26
... Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. 2325 Orchard Parkway San Jose, CA 95131 R ATF1504ASV(L) 26 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER E1 E ...
Page 27
... Lead coplanarity is 0.004" (0.102 mm) maximum. 2325 Orchard Parkway San Jose, CA 95131 R 1409J–PLD–6/05 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER TITLE 84J, 84-lead, Plastic J-leaded Chip Carrier (PLCC) ATF1504ASV(L) 0.318(0.0125) 0.191(0.0075) D2/ COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX A 4.191 – ...
Page 28
... PQFP PIN 1 ID PIN 0º~7º C 2325 Orchard Parkway San Jose, CA 95131 R ATF1504ASV( TITLE 100Q1, 100-lead Body, 3.2 mm Footprint, 0.65 mm Pitch, Plastic Quad Flat Package (PQFP) COMMON DIMENSIONS (Unit of Measure = mm) JEDEC STANDARD MS-022, GC-1 MIN MAX NOTE SYMBOL NOM A – ...
Page 29
... Orchard Parkway San Jose, CA 95131 R 1409J–PLD–6/05 B PIN 1 IDENTIFIER TITLE 100A, 100-lead Body Size, 1.0 mm Body Thickness, 0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) ATF1504ASV( COMMON DIMENSIONS (Unit of Measure = mm) MIN SYMBOL NOM A – – A1 0.05 – ...
Page 30
... Revision History ATF1504ASV(L) 30 Revision Comments Green package options added. 1409J 1409J–PLD–6/05 ...
Page 31
... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...