ATF1508ASV-15AU100 Atmel, ATF1508ASV-15AU100 Datasheet

IC CPLD 15NS LOW V 100TQFP

ATF1508ASV-15AU100

Manufacturer Part Number
ATF1508ASV-15AU100
Description
IC CPLD 15NS LOW V 100TQFP
Manufacturer
Atmel
Series
ATF1508ASV(L)r
Datasheet

Specifications of ATF1508ASV-15AU100

Programmable Type
In System Programmable (min 10K program/erase cycles)
Delay Time Tpd(1) Max
15.0ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Macrocells
128
Number Of I /o
80
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Voltage
3.3V
Memory Type
EEPROM
Number Of Product Terms Per Macro
40
Maximum Operating Frequency
100 MHz
Delay Time
15 ns
Number Of Programmable I/os
80
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
For Use With
ATF15XX-DK3 - KIT DEV FOR ATF15XX CPLD'S
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Number Of Logic Elements/cells
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATF1508ASV-15AU100
Manufacturer:
ATMEL
Quantity:
138
Part Number:
ATF1508ASV-15AU100
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
ATF1508ASV-15AU100
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
ATF1508ASV-15AU100-T
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Features
Enhanced Features
High-density, High-performance, Electrically-erasable
Complex Programmable Logic Device
Flexible Logic Macrocell
Advanced Power Management Features
Available in Commercial and Industrial Temperature Ranges
Available in 84-lead PLCC and 100-lead PQFP and TQFP and
160-lead PQFP Packages
Advanced EE Technology
JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported
Fast In-System Programmability (ISP) via JTAG
PCI-compliant
Security Fuse Feature
Green (Pb/Halide-free/RoHS Compliant) Package Options
Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)
Output Enable Product Terms
Transparent-latch Mode
Combinatorial Output with Registered Feedback within Any Macrocell
Three Global Clock Pins
ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O
Fast Registered Input from Product Term
Programmable “Pin-keeper” Option
V
Pull-up Option on JTAG Pins TMS and TDI
Advanced Power Management Features
CC
– 3.0V to 3.6V Operating Range
– 128 Macrocells
– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell
– 84, 100, 160 Pins
– 15 ns Maximum Pin-to-pin Delay
– Registered Operation up to 77 MHz
– Enhanced Routing Resources
– D/T/Latch Configurable Flip-flops
– Global and Individual Register Control Signals
– Global and Individual Output Enable
– Programmable Output Slew Rate
– Programmable Output Open Collector Option
– Maximum Logic Utilization by Burying a Register within a COM Output
– Automatic 5 µA Standby for “L” Version
– Pin-controlled 100 µA Standby Mode
– Programmable Pin-keeper Inputs and I/Os
– Reduced-power Feature per Macrocell
– 100% Tested
– Completely Reprogrammable
– 10,000 Program/Erase Cycles
– 20 Year Data Retention
– 2000V ESD Protection
– 200 mA Latch-up Immunity
– Edge-controlled Power-down “L”
– Individual Macrocell Power Option
– Disable ITD on Global Clocks, Inputs and I/O for “Z” Parts
Power-up Reset Option
High-
performance
EE PLD
ATF1508ASV
ATF1508ASVL
Rev. 1408H–PLD–7/05
1

Related parts for ATF1508ASV-15AU100

ATF1508ASV-15AU100 Summary of contents

Page 1

... Pull-up Option on JTAG Pins TMS and TDI • Advanced Power Management Features – Edge-controlled Power-down “L” – Individual Macrocell Power Option – Disable ITD on Global Clocks, Inputs and I/O for “Z” Parts High- performance EE PLD ATF1508ASV ATF1508ASVL Rev. 1408H–PLD–7/05 1 ...

Page 2

... I/O/TDI 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 GND 11 I/O 12 I/O 13 I/O 14 I/O/TMS 15 I/O 16 I/O 17 VCCIO 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 I/O 24 I/O 25 ATF1508ASV( I/O I I/O I GND I/O/PD1 3 71 I/O/TDO I I/O VCCIO 5 69 I/O I/O/TDI 6 68 I/O I I/O I VCCIO I I/O I I/O I/O ...

Page 3

... Block Diagram 1408H–PLD–7/05 ATF1508ASV(L) 3 ...

Page 4

... Unused macrocells are automatically disabled by the compiler to decrease power con- sumption. A security fuse, when programmed, protects the contents of the ATF1508ASV(L). Two bytes (16 bits) of User Signature are accessible to the user for purposes such as storing project name, part number, revision or date. The User Signa- ture is accessible regardless of the state of the security fuse ...

Page 5

... Figure 1. ATF1508ASV(L) Macrocell 1408H–PLD–7/05 The ATF1508ASV(L)’s flip-flop has very flexible data and control functions. The data input can come from either the XOR gate, from a separate product term or directly from the I/O pin. Selecting the separate product term allows creation of a buried registered feedback within a combinatorial output macrocell ...

Page 6

... Extra Feedback I/O Control Global Bus/Switch Matrix Foldback Bus Open-collector Output Option ATF1508ASV(L) 6 The ATF15xxSE Family macrocell output can be selected as registered or combinato- rial. The extra buried feedback signal can be either combinatorial or a registered signal regardless of whether the output is combinatorial or registered. (This enhancement function is automatically implemented by the fitter software ...

Page 7

... Management 1408H–PLD–7/05 The ATF1508ASV(L) offers the option of programming all input and I/O pins so that “pin- keeper” circuits can be utilized. When any pin is driven high or low and then subse- quently left floating, it will stay at that previous high- or low-level. This circuitry prevents unused input and I/O lines from floating to intermediate voltage levels, which causes unnecessary power consumption and system noise ...

Page 8

... ATF1508ASV(L) designs are supported by several third-party tools. Automated fitters allow logic synthesis using a variety of high-level description languages and formats. The ATF1508ASV is designed with a power-up reset, a feature critical for state machine initialization point delayed slightly from V tialized, and the state of each output will depend on the polarity of its buffer. However, ...

Page 9

... JTAG protocol. This capability eliminates package handling normally required for pro- gramming and facilitates rapid design iterations and field changes ATF1508ASV(L) via the PC. ISP is performed by using either a download cable, a com- parable board tester or a simple microprocessor interface. To allow ISP programming support by the Automated Test Equipment (ATE) vendors, Serial Vector Format (SVF) files can be created by the Atmel ISP software ...

Page 10

... ON. CC3 Pin Capacitance I/O Note: Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. The OGI pin (high-voltage pin during programming) has a maximum capacitance of 12 pF. ATF1508ASV(L) 10 Condition GND ...

Page 11

... FIN Foldback Term Delay t SEXP ATF1508ASV(L) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied ...

Page 12

... OD1 (Slow slew rate = OFF; V Output Buffer and Pad Delay t OD2 (Slow slew rate = OFF; V Output Buffer and Pad Delay t OD3 (Slow slew rate = ON; V Output Buffer Enable Delay t ZX1 (Slow slew rate = OFF; V ATF1508ASV( 5V pF) CCIO L = 3.3V pF) CCIO 3.3V pF) CCIO L = 5.0V ...

Page 13

... The t parameter must be added to the t RPA power mode. 1408H–PLD–7/05 = 3.3V pF) CCIO L = 5.0V/3.3V pF) CCIO L ( and t LAD LAC TIC ACL Input Test Waveforms and Measurement Levels 1.5 ns typical R F ATF1508ASV(L) -15 -20 Min Max Min parameters for macrocells running in the reduced- SEXP ...

Page 14

... Output AC Test Loads 703 8060 The ATF1508ASV(L) includes two pins for optional pin-controlled power-down feature. When this mode is enabled, the PD pin acts as the power-down pin. When the PD1 and PD2 pin is high, the device supply current is reduced to less than 5 mA. During power- down, all output data and internal logic states are latched and held ...

Page 15

... Cell (BSC) Testing BSC Configuration Pins and Macrocells (Except JTAG TAP Pins) Note: The ATF1508ASV(L) has pull-up option on TMS and TDI pins. This feature is selected as a design option. 1408H–PLD–7/05 The JTAG-BST (JTAG boundary-scan testing) is controlled by the Test Access Port (TAP) controller in the ATF1508ASV(L) ...

Page 16

... BSC Configuration for Macrocell OEJ OUTJ TDI ATF1508ASV(L) 16 These are now available in all package types via the Atmel web site. These models can be used for Boundary-scan Test Operation in the ATF1508ASV(L) and have been scheduled to conform to the IEEE 1149.1 standard. Pin BSC 0 Pin 1 TDI ...

Page 17

... ATF1508ASV(L) Dedicated Pinouts Dedicated Pin 84-lead J-lead INPUT/OE2/GCLK2 INPUT/GCLR INPUT/OE1 INPUT/GCLK1 I/O/GCLK3 I/O/PD (1, 2) I/O/TDI(JTAG) I/O/TMS(JTAG) I/O/TCK(JTAG) I/O/TDO(JTAG) 7,19,32,42, GND 47,59,72,82 3,13,26,38, VCC 43,53,66,78 N SIGNAL PINS # USER I/O PINS OE (1, 2) Global OE pins GCLR Global Clear pin GCLK ( Global Clock pins PD (1, 2) ...

Page 18

... ATF1508ASV(L) I/O Pinouts 84-lead 100-lead MC PLB J-lead PQFP PD1 100 TDI ATF1508ASV(L) 18 100-lead 160-lead TQFP PQFP MC PLB 2 160 159 158 36 C 100 153 152 151 150 149 147 146 145 144 48 TMS 84-lead 100-lead 100-lead 160-lead J-lead PQFP TQFP PQFP - 27 25 ...

Page 19

... ATF1508ASV(L) I/O Pinouts (Continued) 84-lead 100-lead MC PLB J-lead PQFP PD2 TCK 1408H–PLD–7/05 100-lead 160-lead TQFP PQFP MC PLB 100 42 65 101 44 67 102 - - 103 45 68 104 46 69 105 - - 106 47 70 107 - 71 108 48 72 109 49 73 110 - - 111 112 TDO 52 80 ...

Page 20

... LOW POWER ("L") MODE (T = 25° 2.50 2.75 3.00 3.25 SUPPLY VOLTAGE (V) ATF1508ASV(L) 20 REDUCED POWER 3.50 3.75 4.00 = 25°C) 80.00 100.00 3.50 3.75 4.00 SUPPLY CURRENT VS. SUPPLY VOLTAGE PIN-CONTROLLED POWER-DOWN MODE (T = 25° 800 STANDARD & REDUCED POWER MODE 700 600 ...

Page 21

... INPUT VOLTAGE (V) 1408H–PLD–7/05 = 25°C) A 3.75 4.00 = 0.5V 25°C) A 3.75 4.00 = 25°C) A -0.3 -0.2 -0.1 0 ATF1508ASV(L) OUTPUT SOURCE CURRENT VS. OUTPUT VOLTAGE (V = 3.3V,T = 25° -10 -20 -30 -40 -50 -60 -70 0.0 0.5 1.0 1.5 2.0 2.5 3.0 OUTPUT VOLTAGE (V) OUTPUT SINK CURRENT VS ...

Page 22

... There is very little risk in using “C” devices for industrial applications because the V the same for commercial and industrial (there is only 15 C difference at the high end of the temperature range). To use commercial product for industrial temperature ranges, de-rate I ATF1508ASV(L) Green Package Options (Pb/Halide-free/RoHS Compliant ...

Page 23

... Lead coplanarity is 0.004" (0.102 mm) maximum. 2325 Orchard Parkway San Jose, CA 95131 R 1408H–PLD–7/05 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER TITLE 84J, 84-lead, Plastic J-leaded Chip Carrier (PLCC) ATF1508ASV(L) 0.318(0.0125) 0.191(0.0075) D2/ COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX SYMBOL A 4.191 – ...

Page 24

... PQFP PIN 1 ID PIN 0º~7º C 2325 Orchard Parkway San Jose, CA 95131 R ATF1508ASV( TITLE 100Q1, 100-lead Body, 3.2 mm Footprint, 0.65 mm Pitch, Plastic Quad Flat Package (PQFP) COMMON DIMENSIONS (Unit of Measure = mm) JEDEC STANDARD MS-022, GC-1 SYMBOL MIN NOM MAX NOTE A – ...

Page 25

... Orchard Parkway San Jose, CA 95131 R 1408H–PLD–7/05 B PIN 1 IDENTIFIER TITLE 100A, 100-lead Body Size, 1.0 mm Body Thickness, 0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) ATF1508ASV( COMMON DIMENSIONS (Unit of Measure = mm) MIN SYMBOL NOM A – – A1 0.05 – ...

Page 26

... PQFP Dimensions in Millimeters and (Inches). Controlling dimension: Millimeters. JEDEC Standard MS-022 DC-1 PIN 1 ID 0.65(0.0256)BSC 0.23(0.009) 0.11(0.004) 2325 Orchard Parkway San Jose, CA 95131 R ATF1508ASV(L) 26 31.45(1.238) SQ 30.95(1.218) PIN 1 28.10(1.106) SQ 27.90(1.098) 0º~7º 1.03(0.041) 0.50(0.020) 0.73(0.029) 0.25(0.010) TITLE 160Q, 160-lead Body, 3.2 mm Footprint, ...

Page 27

... Revision History 1408H–PLD–7/05 Revision Comments Corrected list of last buy parts. 1408H Green package options added. 1408G ATF1508ASV(L) 27 ...

Page 28

... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...

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