ATF2500C-20JC Atmel, ATF2500C-20JC Datasheet

IC CPLD EE 20NS 44PLCC

ATF2500C-20JC

Manufacturer Part Number
ATF2500C-20JC
Description
IC CPLD EE 20NS 44PLCC
Manufacturer
Atmel
Series
ATF2500C(L)r
Datasheet

Specifications of ATF2500C-20JC

Programmable Type
In System Programmable
Delay Time Tpd(1) Max
20.0ns
Voltage Supply - Internal
4.75 V ~ 5.25 V
Number Of Macrocells
24
Number Of I /o
24
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
44-PLCC
Voltage
5V
Memory Type
EEPROM
Package
44PLCC
Family Name
ATF2500C
Device System Gates
2500
Maximum Propagation Delay Time
20 ns
Number Of User I/os
24
Typical Operating Supply Voltage
5 V
Maximum Operating Frequency
50 MHz
Number Of Product Terms Per Macro
12
Delay Time
20 ns
Number Of Programmable I/os
23
Operating Supply Voltage
5 V
Supply Current
80 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (max)
5.25 V
Supply Voltage (min)
4.75 V
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Number Of Logic Elements/cells
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATF2500C-20JC
Manufacturer:
ST
Quantity:
1 109
Part Number:
ATF2500C-20JC
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
ATF2500C-20JC
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Features
1. Description
The ATF2500C is the highest-density PLD available in a 44-pin surface mount pack-
age. With its fully connected logic array and flexible macrocell structure, high gate
utilization is easily obtainable. The ATF2500C is a high-performance CMOS (electri-
cally-erasable) programmable logic device (PLD) that utilizes Atmel’s proven
electrically-erasable technology. This PLD is now available in a fully Green or LHF
(lead and halide-free) packages.
Figure 1-1.
High-performance, High-density, Electrically-erasable Programmable Logic Device
Fully Connected Logic Array with 416 Product Terms
15 ns Maximum Pin-to-pin Delay for 5V Operation
24 Flexible Output Macrocells
D- or T-type Flip-flops
Product Term or Direct Input Pin Clocking
Registered or Combinatorial Internal Feedback
Backward Compatible with ATV2500B/BQ and ATV2500H Software
Advanced Electrically-erasable Technology
44-lead Surface Mount Package and 40-pin DIP Package
Flexible Design: Up to 48 Buried Flip-flops and 24 Combinatorial Outputs
Simultaneously
8 Synchronous Product Terms
Individual Asynchronous Reset per Macrocell
OE Control per Macrocell
Functionality Equivalent to ATV2500B/BQ and ATV2500H
2000V ESD Protection
Security Fuse Feature to Protect the Code
Commercial, Industrial and Military Temperature Range Offered
10 Year Data Retention
Pin Keeper Option
200 mA Latch-up Immunity
Green Package Options (Pb/Halide-free/RoHS Compliant) Available
– 48 Flip-flops – Two per Macrocell
– 72 Sum Terms
– All Flip-flops, I/O Pins Feed in Independently
– Reprogrammable
– 100% Tested
Block Diagram
ATF2500C
CPLD Family
Datasheet
ATF2500C
0777K–PLD–1/24/08

Related parts for ATF2500C-20JC

ATF2500C-20JC Summary of contents

Page 1

... Green Package Options (Pb/Halide-free/RoHS Compliant) Available 1. Description The ATF2500C is the highest-density PLD available in a 44-pin surface mount pack- age. With its fully connected logic array and flexible macrocell structure, high gate utilization is easily obtainable. The ATF2500C is a high-performance CMOS (electri- cally-erasable) programmable logic device (PLD) that utilizes Atmel’ ...

Page 2

... The ATF2500C is organized around a single universal array. All pins and feedback terms are always available to every macrocell. Each of the 38 logic pins are array inputs, as are the out- puts of each flip-flop. In the ATF2500C, four product terms are input to each sum term. Furthermore, each macrocell’s three sum terms can be combined to provide product terms per sum term with no per- formance penalty ...

Page 3

... A Total of 48 Registers – The ATF2500C provides two flip-flops per macrocell – a total of 48. Each register has its own clock and reset terms, as well as its own sum term. ...

Page 4

... Power-up Reset The registers in the ATF2500Cs are designed to reset during power-up point delayed slightly from V depend on the polarity of the output buffer. This feature is critical for state as nature of reset and the uncertainty of how V the system, the following conditions are required: 1. The V 2. After reset occurs, all input and feedback setup times must be met before driving the clock pin or terms high, and 3 ...

Page 5

... Preload and Observability of Registered Outputs The ATF2500Cs registers are provided with circuitry to allow loading of each register asynchro- nously with either a high or a low. This feature will simplify testing since any state can be forced into the registers to control test sequencing priate register high settings ...

Page 6

... Additionally, the ATF2500C may be programmed to perform the ATV2500Hs functional subset (no T-type flip-flops, pin clocking or D/T2 feedback) using the ATV2500H JEDEC file. In this case, the ATF2500C becomes a direct replacement or speed upgrade for the ATV2500H. The ATF2500C are direct replacements for the ATV2500B/BQ and the ATV2500H, including the lack of extra grounds on P4 and P26 ...

Page 7

... Security Fuse Usage A single fuse is provided to prevent unauthorized copying of ATF2500C fuse patterns. Once pro- grammed, the outputs will read programmed during verify. The security fuse should be programmed last, as its effect is immediate. The security fuse also inhibits Preload and Q2 observability. 8. Bus-friendly Pin-keeper Input and I/O All ATF2500C family members have programmable internal input and I/O pin-keeper circuits ...

Page 8

... Q1 true and false, and the pin true and false. The positions occupied by these signals in the global bus are the six numbers in the bus diagram next to each macrocell. Note: ATF2500C 8 I/O Diagram INPUT 1. Either the flip-flop input (D/T2) or output (Q2) may be fed back in the ATF2500Cs. PROGRAMMABLE OPTION (1) true 0777K–PLD–1/24/08 ...

Page 9

... Functional Logic Diagram ATF2500C Notes: 1. Pin 4 and Pin 26 are “ground” connections and are not required for PLCC, LCC and JLCC versions of ATF2500C, making them compatible with ATV2500H, ATV2500B and ATV2500BQ pinouts. 2. For DIP package, VCC = P10 and GND = P30. For, PLCC, LCC and JLCC packages, VCC = P11 and P12, GND = P33 and P34, and GND = P4, P26 (See Note 1, above). 0777K– ...

Page 10

... Output Logic, Registered 9.3 Output Logic, Combinatorial Note: 1. These diagrams show equivalent logic functions, not necessarily the actual circuit implementation. ATF2500C 10 ( Output S3 Configuration 0 Active Low 1 Active High S4 Register 1 Type ( Note: 1. These four terms are shared with D/T1. Figure 9-1. Terms in ...

Page 11

... Temperature Under Bias................................ -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C Junction Temperature ............................................. 150°C Max Voltage on Any Pin with Respect to Ground .........................................-2.0V to +7.0V 11. DC and AC Operating Conditions Operating Temperature V Power Supply CC 11.1 ATF2500C DC Characteristics Symbol Parameter Condition I Input Load Current V IL Output Leakage I V ...

Page 12

... AC Waveforms Input Pin Clock (1) 11.3 AC Waveforms Product Term Clock (1) 11.4 AC Waveforms Combinatorial Outputs and Feedback Note: 1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified. ATF2500C 12 0777K–PLD–1/24/08 ...

Page 13

... EA2 t Feedback to Output Disable ER2 t Asynchronous Reset Width AW t Asynchronous Reset to Registered Output AP t Asynchronous Reset to Registered Feedback APF 11.6 ATF2500C Register AC Characteristics, Input Pin Clock Symbol Parameter t Clock to Output COS t Clock to Feedback CFS t Input Setup Time SIS t Feedback Setup Time ...

Page 14

... ATF2500C Register AC Characteristics, Product Term Clock Symbol Parameter t Clock to Output COA t Clock to Feedback CFA t Input Setup Time SIA t Feedback Setup Time SFA t Hold Time HA t Clock Width WA t Clock Period PA External Feedback 1/(t SIA F Internal Feedback 1/(t MAXA SFA No Feedback 1/(t ...

Page 15

... TEMPERATURE (°C) STAND- SUPPLY VOLTAGE (T 100.0 90.0 80.0 70.0 60.0 50.0 4.5 4.8 5.0 5.3 SUPPLY VOLTAGE (V) ATF2500C INPUT CLAMP CURRENT VS. INPUT VOLTAGE (V = 5.0V -50 -100 -150 -200 -1.4 -1.2 -1.0 -0.8 -0.6 -0.4 INPUT VOLTAGE (V) A TF2500C VS. ...

Page 16

... ATF2500C OUTPUT SOURCE CURRENT VS. OUTPUT VOLTAGE ( 4.5 4.6 4.7 Output Voltage (V) ATF2500C OUTPUT SINK CURRENT VS. OUTPUT VOLTAGE ( 0.0 0.1 0.2 0.3 0.4 0.5 0.6 OUTPUT VOLTAGE (V) ATF2500C SUPPLY CURRENT VS. SUPPLY VOLTAGE (Freq MHz, T 100 4.50 4.75 5.00 Supply Voltage (V) ATF2500C SUPPLY CURRENT VS. ...

Page 17

... ATF2500C NORMALIZED T VS. AMBIENT TEMP SIS (V = 5V) CC 25.0 AMBIENT TEMPERATURE (°C) NORMALIZED T VS. SUPPLY VOLTAGE SIA (T = 25°C) A 4.75 5.00 5.25 SUPPLY VOLTAGE (V) NORMALIZED T VS ...

Page 18

... Wide, Plastic, Dual Inline Package (PDIP) 44J 44-lead, Plastic J-leaded Chip Carrier (PLCC) 44K 44-lead, Non-windowed, Ceramic J-leaded Chip Carrier (JLCC) ATF2500C 18 Ordering Code ATF2500C-15JC ATF2500C-15JI ATF2500C-20JC ATF2500C-20PC ATF2500C-20JI ATF2500C-20PI Ordering Code ATF2500C-20KM ATF2500C-20GM Ordering Code ATF2500C-15JU ATF2500C-20PU Package Type ...

Page 19

... San Jose, CA 95131 R 0777K–PLD–1/24/08 53.09(2.090) 51.82(2.040) 48.26(1.900) REF 1.65(0.065) 1.14(0.045) 15.70(0.620) 15.00(0.590) 0.20(0.008) TITLE 40D6, 40-lead, 0.600" Wide, Non-windowed, Ceramic Dual Inline Package (Cerdip) ATF2500C PIN 1 15.49(0.610) 12.95(0.510) 0.127(0.005)MIN 1.78(0.070) 0.38(0.015) 0.66(0.026) 0.36(0.014) 0º~ 15º REF 17.80(0.700) MAX DRAWING NO. 40D6 10/23/03 REV ...

Page 20

... PDIP A SEATING PLANE Notes: 1. This package conforms to JEDEC reference MS-011, Variation AC. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). 2325 Orchard Parkway San Jose, CA 95131 R ATF2500C 20 D PIN 0º ~ 15º REF eB TITLE 40P6, 40-lead (0.600" ...

Page 21

... Lead coplanarity is 0.004" (0.102 mm) maximum. 2325 Orchard Parkway San Jose, CA 95131 R 0777K–PLD–1/24/08 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER TITLE 44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC) ATF2500C 0.318(0.0125) 0.191(0.0075) D2/ COMMON DIMENSIONS (Unit of Measure = mm) MIN MAX SYMBOL NOM A 4.191 – ...

Page 22

... JLCC D 1.14 X 45˚ .025(.635) RADIUS MAX (3X) Note : Refer to MIL-STD-1835C-J1 2325 Orchard Parkway San Jose, CA 95131 R 15. Revision History ATF2500C 0. TITLE 44K, 44-lead, Non-windowed, Ceramic J-leaded Chip Carrier (JLCC) 0.89 X 45˚ COMMON DIMENSIONS (Unit of Measure = mm) ...

Page 23

... Revision Level – Release Date History Added fully Green and Military temperatures packages in J – May 2005 on page K – Jan. 2008 Added 40-pin CerDIP Package Option. 0777K–PLD–1/24/08 18. ATF2500C Section 13. ”Ordering Information” 23 ...

Page 24

... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...

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