IC MAX 3000A CPLD 64 44-TQFP

EPM3064ATC44-10N

Manufacturer Part NumberEPM3064ATC44-10N
DescriptionIC MAX 3000A CPLD 64 44-TQFP
ManufacturerAltera
SeriesMAX® 3000A
EPM3064ATC44-10N datasheet
 


Specifications of EPM3064ATC44-10N

Programmable TypeIn System ProgrammableDelay Time Tpd(1) Max10.0ns
Voltage Supply - Internal3 V ~ 3.6 VNumber Of Logic Elements/blocks4
Number Of Macrocells64Number Of Gates1250
Number Of I /o34Operating Temperature0°C ~ 85°C
Mounting TypeSurface MountPackage / Case44-TQFP, 44-VQFP
Voltage3.0 V ~ 3.6 VMemory TypeEEPROM
Number Of Logic Elements/cells4Lead Free Status / RoHS StatusLead free / RoHS Compliant
Features-Other names544-1977
EPM3064ATC44-10N
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June 2006, ver. 3.5
Features...
Table 1. MAX 3000A Device Features
Feature
EPM3032A
Usable gates
600
Macrocells
32
Logic array blocks
2
Maximum user I/O
34
pins
t
(ns)
4.5
PD
t
(ns)
2.9
SU
t
(ns)
3.0
CO1
f
(MHz)
227.3
CNT
Altera Corporation
DS-MAX3000A-3.5
®
High–performance, low–cost CMOS EEPROM–based programmable
logic devices (PLDs) built on a MAX
3.3-V in-system programmability (ISP) through the built–in
IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with
advanced pin-locking capability
ISP circuitry compliant with IEEE Std. 1532
Built–in boundary-scan test (BST) circuitry compliant with
IEEE Std. 1149.1-1990
Enhanced ISP features:
Enhanced ISP algorithm for faster programming
ISP_Done bit to ensure complete programming
Pull-up resistor on I/O pins during in–system programming
High–density PLDs ranging from 600 to 10,000 usable gates
4.5–ns pin–to–pin logic delays with counter frequencies of up to
227.3 MHz
TM
MultiVolt
I/O interface enabling the device core to run at 3.3 V,
while I/O pins are compatible with 5.0–V, 3.3–V, and 2.5–V logic
levels
Pin counts ranging from 44 to 256 in a variety of thin quad flat pack
(TQFP), plastic quad flat pack (PQFP), plastic J–lead chip carrier
TM
(PLCC), and FineLine BGA
Hot–socketing support
Programmable interconnect array (PIA) continuous routing structure
for fast, predictable performance
Industrial temperature range
EPM3064A
EPM3128A
1,250
2,500
64
128
4
8
66
98
4.5
5.0
2.8
3.3
3.1
3.4
222.2
192.3
MAX 3000A
Programmable Logic
Device Family
Data Sheet
®
architecture (see
Table
packages
EPM3256A
EPM3512A
5,000
10,000
256
512
16
161
208
7.5
7.5
5.2
5.6
4.8
4.7
126.6
116.3
1)
32
1

EPM3064ATC44-10N Summary of contents

  • Page 1

    ... CO1 f (MHz) 227.3 CNT Altera Corporation DS-MAX3000A-3.5 ® High–performance, low–cost CMOS EEPROM–based programmable logic devices (PLDs) built on a MAX 3.3-V in-system programmability (ISP) through the built–in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability – ...

  • Page 2

    ... Programmable output slew–rate control Software design support and automatic place–and–route provided by Altera’s development systems for Windows–based PCs and Sun SPARCstations, and HP 9000 Series 700/800 workstations Additional design entry and simulation support provided by EDIF and netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from third– ...

  • Page 3

    ... The devices can be reprogrammed for quick and efficient iterations during design development and debugging cycles, and can be programmed and erased up to 100 times. Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Table 2. MAX 3000A Speed Grades Device – ...

  • Page 4

    ... MAX 3000A devices to be used in mixed–voltage systems. MAX 3000A devices are supported by Altera development systems, which are integrated packages that offer schematic, text—including VHDL, Verilog HDL, and the Altera Hardware Description Language (AHDL)— ...

  • Page 5

    ... The MAX 3000A device architecture is based on the linking of high–performance LABs. LABs consist of 16–macrocell arrays, as shown in that is fed by all dedicated input pins, I/O pins, and macrocells. Each LAB is fed by the following signals: ■ ■ Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet LAB ...

  • Page 6

    ... Two kinds of expander product terms (“expanders”) are available to supplement macrocell logic resources: ■ ■ The Altera development system automatically optimizes product–term allocation according to the logic requirements of the design. 6 Figure 2 Global Clear ...

  • Page 7

    ... operation with programmable clock control. The flipflop can be bypassed for combinatorial operation. During design entry, the designer specifies the desired flipflop type; the Altera development system software then selects the most efficient flipflop operation for each registered function to optimize resource utilization. ...

  • Page 8

    ... Shareable expanders incur a small delay (t macrocells. Figure 3. MAX 3000A Shareable Expanders 8 ). Figure 3 shows how shareable expanders can feed multiple SEXP Shareable expanders can be shared by any or all macrocells in an LAB. 36 Signals 16 Shared from PIA Expanders Macrocell Product-Term Logic Product-Term Select Matrix Macrocell Product-Term Logic Altera Corporation ...

  • Page 9

    ... OR logic, with five product terms provided by the macrocell and 15 parallel expanders provided by neighboring macrocells in the LAB. The Altera development system compiler can automatically allocate up to three sets five parallel expanders to the macrocells that require additional product terms. Each set of five parallel expanders incurs a ...

  • Page 10

    ... PIA signal to drive into the LAB. 10 From Previous Macrocell Product- er Select Matrix Product- Ter Select Matrix To Next Macrocell Figure 5 shows how the PIA signals are routed Preset Macrocell Product- Term Logic Clock Clear Preset Macrocell Product- Term Logic Clock Clear Altera Corporation ...

  • Page 11

    ... MAX 3000A devices. The I/O control block has global output enable signals that are driven by the true or complement of two output enable signals, a subset of the I/O pins subset of the I/O macrocells. Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet PIA Signals To LAB ...

  • Page 12

    ... When an I/O pin is configured as an input, the associated macrocell can be used for buried logic Global Output Enable Signals (1) VCC to Other I/O Pins GND from Macrocell Open-Drain Output Slew-Rate Control to PIA OE Select Multiplexer , the output is CC Altera Corporation ...

  • Page 13

    ... The ISP circuitry in MAX 3000A devices is compliant with the IEEE Std. 1532 specification. The IEEE Std. 1532 is a standard developed to allow concurrent ISP between multiple PLD vendors. Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Application Note 88 (Using the Jam Language for ISP & ICR via Processor), Application Note 122 (Using Jam STAPL for ISP & ...

  • Page 14

    ... EEPROM cells. This process is repeated for each EEPROM address. Verify. Verifying an Altera device in-system involves shifting in addresses, applying the read pulse to verify the EEPROM cells, and shifting out the data for comparison. This process is repeated for each EEPROM address ...

  • Page 15

    ... The time required to program a single MAX 3000A device in-system can be calculated from the following formula: t PROG where: t The ISP times for a stand-alone verification of a single MAX 3000A device can be calculated from the following formula: t VER where: t Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Cycle PTCK = t + ------------------------------- - PPULSE f ...

  • Page 16

    ... Altera Corporation Units Units ...

  • Page 17

    ... MAX 3000A devices include the JTAG BST circuitry defined by IEEE Std. 1149.1–1990. 1149.1 (JTAG) MAX 3000A devices. The pin-out tables found on the Altera web site (http://www.altera.com) or the Altera Digital Library show the location of Boundary–Scan the JTAG control pins for each device. If the JTAG interface is not Support required, the JTAG pins are available as user I/O pins ...

  • Page 18

    ... The most significant bit (MSB the left. The least significant bit (LSB) for all JTAG IDCODEs is 1. Application Note 39 (IEEE 1149.1 (JTAG) Boundary–Scan Testing in Altera for more information on JTAG BST. Tables 8 and Boundary–Scan Register Length ...

  • Page 19

    ... Figure 7 Figure 7. MAX 3000A JTAG Waveforms Captured Table 10 devices. Symbol Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet shows the timing information for the JTAG signals. TMS TDI t JCP t t JCH JCL TCK t JPZX TDO t JSSU Signal JSZX Signal ...

  • Page 20

    ... When MAX 3000A device can drive a 2.5–V device that has 3.3–V CCIO tolerant inputs. ) for the t LPA LAD levels lower than 3.0 V CCIO instead of t OD2 OD1 Output Signal (V) 3.3 5.0 2.5 3 Altera Corporation , LAC IC . Inputs can 5.0 v ...

  • Page 21

    ... EEPROM bit and all internal logic elements ensures 100% programming yield. AC test measurements are taken under conditions equivalent to those shown in erased during early stages of the production flow. Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet current specification should be OL Figure 8 ...

  • Page 22

    ... Device Output 620 Ω [481 Ω] C1 (includes jig capacitance) Device input rise and fall times < Note (1) Min Max –0.5 4.6 –2.0 5.75 –25 25 –65 150 –65 135 135 Altera Corporation VCC To Test System Unit ° C ° C ° C ...

  • Page 23

    ... I I Tri–state output off–state current OZ R Value of I/O pin pull–up resistor when programming in–system or during power–up Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Conditions (10) (3) Commercial range Industrial range Commercial range Industrial range (11) ...

  • Page 24

    ... I/O pin capacitance I/O Notes to tables: (1) See the Operating Requirements for Altera Devices Data (2) Minimum DC input voltage is –0.5 V. During transitions, the inputs may undershoot to –2 overshoot to 5.75 V for input currents less than 100 mA and periods shorter than 20 ns. (3) All pins, including dedicated inputs, I/O pins, and JTAG pins, may be driven before V powered ...

  • Page 25

    ... Signals can be driven into MAX 3000A devices before and during power-up without damaging the device. In addition, MAX 3000A devices do not drive out during power-up. Once operating conditions are reached, MAX 3000A devices operate as specified by the user. Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet 3.3 V 150 ...

  • Page 26

    ... MAX 3000A Programmable Logic Device Family Data Sheet Timing Model MAX 3000A device timing can be analyzed with the Altera software, with a variety of popular industry–standard EDA simulators and timing analyzers, or with the timing model shown in devices have predictable internal delays that enable the designer to determine the worst– ...

  • Page 27

    ... All timing characteristics are measured at 1.5 V. Shared Expander Parallel Expander Data or Enable (Logic Array Output) Input or I/O Pin Register to PIA Register Output Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Combinatorial Mode t IN Input Pin t IO I/O Pin PIA Delay ...

  • Page 28

    ... Altera Corporation Unit MHz ns MHz ...

  • Page 29

    ... Array clock delay IC t Register enable time EN t Global control delay GLOB t Register preset time PRE t Register clear time CLR Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Note (1) Conditions –4 Min Max 0.7 0.7 1.9 0.5 1.5 0.6 0 ...

  • Page 30

    ... Altera Corporation Unit ns ns Unit MHz ns MHz ...

  • Page 31

    ... Combinatorial delay COMB t Array clock delay IC t Register enable time EN t Global control delay GLOB t Register preset time PRE Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Note (1) Conditions –4 Min Max 0.6 0.6 1.8 0.4 1.5 0.6 0 ...

  • Page 32

    ... Altera Corporation Unit 2.9 ns 2.3 ns 5.0 ns Unit Max 6 9 10.2 ns MHz 10 ...

  • Page 33

    ... V = 2.5 V CCIO t Output buffer enable delay, ZX3 slow slew rate = 2 3.3 V CCIO t Output buffer disable delay Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Note (1) Conditions –5 Min Max (2), (4) 192.3 Conditions –5 Min Max ...

  • Page 34

    ... Speed Grade –10 Max Min Max 7.5 10 7.5 10 6.9 0.0 4.8 1.0 6.4 4.0 4.0 3.6 0.5 7.3 1.0 9.7 4.0 4.0 4.0 Altera Corporation Unit Unit ...

  • Page 35

    ... 3.3 V CCIO t Output buffer enable delay, slow ZX1 slew rate = off V CCIO t Output buffer enable delay, slow ZX2 slew rate = off V CCIO Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Note (1) Conditions Min (2) (2), (4) 126.6 (2) (2), (4) 126.6 Conditions ...

  • Page 36

    ... Max 9.0 10.0 ns 4.0 5.0 ns 2.9 ns 1.2 ns 1.2 1.6 ns 0.8 1.2 ns 1.6 2.1 ns 1.0 1.3 ns 1.5 2.0 ns 2.3 3.0 ns 2.3 3.0 ns 2.4 3.2 ns 4.0 5.0 ns Unit -10 Min Max 10.0 ns 10.0 ns 7.6 ns 0.0 ns 3.0 ns 0.0 ns 1.0 6.3 ns 4.0 ns 4.0 ns 3.5 ns Altera Corporation ...

  • Page 37

    ... Output buffer and pad delay, OD1 slow slew rate = off V = 3.3 V CCIO t Output buffer and pad delay, OD2 slow slew rate = off V = 2.5 V CCIO Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Note (1) Conditions Speed Grade -7 Min Max (2) 0 (2) 1.0 7 ...

  • Page 38

    ... IC EN SEXP ACL Unit -10 Min Max 6.5 ns 5.0 ns 5.5 ns 10.0 ns 5.0 ns 3.0 ns 0.8 ns 1.6 ns 1.4 ns 1.7 ns 0.8 ns 2.3 ns 1.3 ns 2.2 ns 1.4 ns 1.4 ns 4.0 ns 5.0 ns Table 13 on page 23. See parameter LPA parameter into the signal LAD parameters for macrocells CPPW Altera Corporation ...

  • Page 39

    ... Power Supply power (P) versus frequency (f devices is calculated with the following equation: Consumption The P and switching frequency, can be calculated using the guidelines given in Application Note 74 (Evaluating Power for Altera The I logic. The I I CCINT (A × MC The parameters in the MAX tog Table 26. MAX 3000A I The I conditions using a pattern of a 16– ...

  • Page 40

    ... Frequency (MHz) 40 EPM3064A 227.3 MHz High Speed Typical I CC Active (mA) 144.9 MHz 200 250 192.3 MHz High Speed 108.7 MHz 200 250 3 Room Temperature 60 50 High Speed 40 30 125.0 MHz 20 Low Power 100 200 Frequency (MHz) Altera Corporation 222.2 MHz 250 ...

  • Page 41

    ... Room Temperature 250 200 Typical I CC 150 Active (mA) 100 Low Power Frequency (MHz) Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet EPM3512A 172.4 MHz High Speed Typical I Active (mA) 102.0 MHz 100 200 600 Room Temperature 500 ...

  • Page 42

    ... MAX 3000A Programmable Logic Device Family Data Sheet Device See the Altera web site (http://www.altera.com) or the Altera Digital Library for pin–out information. Pin–Outs Figures 14 MAX 3000A devices. Figure 14. 44–Pin PLCC/TQFP Package Pin–Out Diagram Package outlines not drawn to scale. ...

  • Page 43

    ... Figure 15. 100–Pin TQFP Package Pin–Out Diagram Package outline not drawn to scale. Figure 16. 144–Pin TQFP Package Pin–Out Diagram Package outline not drawn to scale Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Pin 1 EPM3064A EPM3128A Pin 26 . Indicates location ...

  • Page 44

    ... MAX 3000A Programmable Logic Device Family Data Sheet Figure 17. 208–Pin PQFP Package Pin–Out Diagram Package outline not drawn to scale Pin 1 Pin EPM3256A EPM3512A Pin 157 Pin 105 Altera Corporation ...

  • Page 45

    ... The following changes were made in the MAX 3000A Programmable Logic Device Data Sheet version 3.5: ■ Version 3.4 The following changes were made in the MAX 3000A Programmable Logic Device Data Sheet version 3.4: ■ Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet . ...

  • Page 46

    ... Copyright © 2006 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the (408) 544-7000 stylized Altera logo, specific device designations, and all other words and logos that are identified as http://www.altera.com trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Applications Hotline: Corporation in the U ...