EPM3064ATC100-7N Altera, EPM3064ATC100-7N Datasheet - Page 35

• Manufacturer Part Number: EPM3064ATC100-7N
• Description: IC MAX 3000A CPLD 64 100-TQFP
• Manufacturer: Altera
• Series: MAX® 3000Ar

Specifications of EPM3064ATC100-7N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.5ns
• Voltage Supply - Internal: 3 V ~ 3.6 V
• Number Of Logic Elements/blocks: 4
• Number Of Macrocells: 64
• Number Of Gates: 1250
• Number Of I /o: 66
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Voltage: 3.0 V ~ 3.6 V
• Memory Type: EEPROM
• Number Of Logic Elements/cells: 4
• Family Name: MAX 3000A
• # Macrocells: 64
• Number Of Usable Gates: 1250
• Frequency (max): 166.67MHz
• Propagation Delay Time: 7.5ns
• Number Of Logic Blocks/elements: 4
• # I/os (max): 66
• Operating Supply Voltage (typ): 3.3V
• In System Programmable: Yes
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1976; EPM3064ATC100-7N

Altera Corporation
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t
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t
t
t
t
t
t
t
t
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IN
IO
SEXP
PEXP
LAD
LAC
IOE
OD1
OD2
OD3
ZX1
ZX2
CNT
CNT
ACNT
ACNT
Table 22. EPM3256A External Timing Parameters
Table 23. EPM3256A Internal Timing Parameters (Part 1 of 2)
Symbol
Symbol
Input pad and buffer delay
I/O input pad and buffer delay
Shared expander delay
Parallel expander delay
Logic array delay
Logic control array delay
Internal output enable delay
Output buffer and pad delay,
slow slew rate = off
V
Output buffer and pad delay,
slow slew rate = off
V
Output buffer and pad delay,
slow slew rate = on
V
Output buffer enable delay, slow
slew rate = off V
Output buffer enable delay, slow
slew rate = off V
Minimum global clock
period
Maximum internal global
clock frequency
Minimum array clock
period
Maximum internal array
clock frequency
CCIO
CCIO
CCIO
= 3.3 V
= 2.5 V
= 2.5 V or 3.3 V
Parameter
Parameter
CCIO
CCIO
= 3.3 V
= 2.5 V
(2)
(2),
(2)
(2),
Conditions
(4)
(4)
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
MAX 3000A Programmable Logic Device Family Data Sheet
Conditions
Note (1)
126.6
126.6
Min
Min
–7
Note (1)
Max
–7
Speed Grade
7.9
7.9
Max
Speed Grade
0.9
0.9
2.8
0.5
2.2
1.0
0.0
1.2
1.7
6.2
4.0
4.5
95.2
95.2
Min
Min
–10
–10
Max
10.5
10.5
Max
1.2
1.2
3.7
0.6
2.8
1.3
0.0
1.6
2.1
6.6
5.0
5.5
Unit
MHz
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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