EPM3064ATC100-4 Altera, EPM3064ATC100-4 Datasheet - Page 10

• Manufacturer Part Number: EPM3064ATC100-4
• Description: IC MAX 3000A CPLD 64 100-TQFP
• Manufacturer: Altera
• Series: MAX® 3000Ar

Specifications of EPM3064ATC100-4

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 4.5ns
• Voltage Supply - Internal: 3 V ~ 3.6 V
• Number Of Logic Elements/blocks: 4
• Number Of Macrocells: 64
• Number Of Gates: 1250
• Number Of I /o: 66
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Voltage: 3.0 V ~ 3.6 V
• Memory Type: EEPROM
• Number Of Logic Elements/cells: 4
• Family Name: MAX 3000A
• # Macrocells: 64
• Number Of Usable Gates: 1250
• Frequency (max): 250MHz
• Propagation Delay Time: 4.5ns
• Number Of Logic Blocks/elements: 4
• # I/os (max): 66
• Operating Supply Voltage (typ): 3.3V
• In System Programmable: Yes
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: TQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-1157

MAX 3000A Programmable Logic Device Family Data Sheet
Figure 4. MAX 3000A Parallel Expanders
10
Unused product terms in a macrocell can be allocated to a neighboring macrocell.
36 Signals
from PIA
Expanders
16 Shared
Programmable Interconnect Array
Logic is routed between LABs on the PIA. This global bus is a
programmable path that connects any signal source to any destination on
the device. All MAX 3000A dedicated inputs, I/O pins, and macrocell
outputs feed the PIA, which makes the signals available throughout the
entire device. Only the signals required by each LAB are actually routed
from the PIA into the LAB.
into the LAB. An EEPROM cell controls one input to a two-input AND gate,
which selects a PIA signal to drive into the LAB.
Product-
Product-
Select
Matrix
Select
Matrix
Ter
T T m
er
Macrocell
Previous
From
Figure 5
shows how the PIA signals are routed
Macrocell
To Next
Preset
Clock
Clear
Preset
Clock
Clear
Altera Corporation
Macrocell
Product-
Term Logic
Macrocell
Product-
Term Logic