EPM3064ATC100-4 Altera, EPM3064ATC100-4 Datasheet - Page 26

IC MAX 3000A CPLD 64 100-TQFP

EPM3064ATC100-4

Manufacturer Part Number
EPM3064ATC100-4
Description
IC MAX 3000A CPLD 64 100-TQFP
Manufacturer
Altera
Series
MAX® 3000Ar
Datasheet

Specifications of EPM3064ATC100-4

Programmable Type
In System Programmable
Delay Time Tpd(1) Max
4.5ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Logic Elements/blocks
4
Number Of Macrocells
64
Number Of Gates
1250
Number Of I /o
66
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Voltage
3.0 V ~ 3.6 V
Memory Type
EEPROM
Number Of Logic Elements/cells
4
Family Name
MAX 3000A
# Macrocells
64
Number Of Usable Gates
1250
Frequency (max)
250MHz
Propagation Delay Time
4.5ns
Number Of Logic Blocks/elements
4
# I/os (max)
66
Operating Supply Voltage (typ)
3.3V
In System Programmable
Yes
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Package Type
TQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1157

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MAX 3000A Programmable Logic Device Family Data Sheet
Timing Model
Figure 10. MAX 3000A Timing Model
26
Delay
Input
t
I N
Delay
PIA
t
PIA
MAX 3000A device timing can be analyzed with the Altera software, with
a variety of popular industry–standard EDA simulators and timing
analyzers, or with the timing model shown in
devices have predictable internal delays that enable the designer to
determine the worst–case timing of any design. The software provides
timing simulation, point–to–point delay prediction, and detailed timing
analysis for device–wide performance evaluation.
The timing characteristics of any signal path can be derived from the
timing model and parameters of a particular device. External timing
parameters, which represent pin–to–pin timing delays, can be calculated
as the sum of internal parameters.
between internal and external delay parameters.
Expander Delay
Internal Output
Global Control
Control Delay
Enable Delay
Logic Array
Register
Shared
Delay
t
Delay
t
t
t
t
t
t
GLOB
SEXP
LAC
I C
EN
LAD
IOE
Expander Delay
Parallel
t
PEXP
Figure 11
Register
t
t
t
t
t
t
Delay
SU
H
PRE
CLR
RD
COMB
shows the timing relationship
Figure
Output
Delay
t
t
t
t
t
t
t
OD1
OD2
OD3
XZ
Z
Z X2
Z X3
10. MAX 3000A
X1
Altera Corporation
Delay
I/O
t
I O

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