IC MAX 7000 CPLD 64 44-PLCC

EPM7064SLI44-7N

Manufacturer Part NumberEPM7064SLI44-7N
DescriptionIC MAX 7000 CPLD 64 44-PLCC
ManufacturerAltera
SeriesMAX® 7000
EPM7064SLI44-7N datasheet
 

Specifications of EPM7064SLI44-7N

Programmable TypeIn System ProgrammableDelay Time Tpd(1) Max7.5ns
Voltage Supply - Internal4.5 V ~ 5.5 VNumber Of Logic Elements/blocks4
Number Of Macrocells64Number Of Gates1250
Number Of I /o36Operating Temperature-40°C ~ 85°C
Mounting TypeSurface MountPackage / Case44-PLCC
Voltage5VMemory TypeEEPROM
Number Of Logic Elements/cells4Lead Free Status / RoHS StatusLead free / RoHS Compliant
Features-Other names544-2017
EPM7064SLI44-7N
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Page 21
22
Page 22
23
Page 23
24
Page 24
25
Page 25
26
Page 26
27
Page 27
28
Page 28
29
Page 29
30
Page 30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
Page 22/66

Download datasheet (2Mb)Embed
PrevNext
MAX 7000 Programmable Logic Device Family Data Sheet
IEEE Std.
MAX 7000 devices support JTAG BST circuitry as specified by IEEE Std.
1149.1-1990.
1149.1 (JTAG)
MAX 7000 family. The pin-out tables (see the Altera web site
(http://www.altera.com) or the Altera Digital Library for pin-out
Boundary-Scan
information) show the location of the JTAG control pins for each device.
Support
If the JTAG interface is not required, the JTAG pins are available as user
I/O pins.
Table 9. MAX 7000 JTAG Instructions
JTAG Instruction
Devices
SAMPLE/PRELOAD
EPM7128S
EPM7160S
EPM7192S
EPM7256S
EXTEST
EPM7128S
EPM7160S
EPM7192S
EPM7256S
BYPASS
EPM7032S
EPM7064S
EPM7128S
EPM7160S
EPM7192S
EPM7256S
IDCODE
EPM7032S
EPM7064S
EPM7128S
EPM7160S
EPM7192S
EPM7256S
ISP Instructions
EPM7032S
EPM7064S
EPM7128S
EPM7160S
EPM7192S
EPM7256S
22
Table 9
describes the JTAG instructions supported by the
Description
Allows a snapshot of signals at the device pins to be captured and
examined during normal device operation, and permits an initial data
pattern output at the device pins.
Allows the external circuitry and board-level interconnections to be
tested by forcing a test pattern at the output pins and capturing test
results at the input pins.
Places the 1-bit bypass register between the TDI and TDO pins, which
allows the BST data to pass synchronously through a selected device
to adjacent devices during normal device operation.
Selects the IDCODE register and places it between TDI and TDO,
allowing the IDCODE to be serially shifted out of TDO.
These instructions are used when programming MAX 7000S devices
via the JTAG ports with the MasterBlaster, ByteBlasterMV, BitBlaster
download cable, or using a Jam File (.jam), Jam Byte-Code file (.jbc),
or Serial Vector Format file (.svf) via an embedded processor or test
equipment.
Altera Corporation