IC CPLD 1.6K 72MCELL 64-VQFP

XC9572XL-10VQG64C

Manufacturer Part NumberXC9572XL-10VQG64C
DescriptionIC CPLD 1.6K 72MCELL 64-VQFP
ManufacturerXilinx Inc
SeriesXC9500XL
XC9572XL-10VQG64C datasheets
 

Specifications of XC9572XL-10VQG64C

Programmable TypeIn System Programmable (min 10K program/erase cycles)Delay Time Tpd(1) Max10.0ns
Voltage Supply - Internal3 V ~ 3.6 VNumber Of Logic Elements/blocks4
Number Of Macrocells72Number Of Gates1600
Number Of I /o52Operating Temperature0°C ~ 70°C
Mounting TypeSurface MountPackage / Case64-TQFP, 64-VQFP
Voltage3.3VMemory TypeFLASH
Dc1017For Use With122-1512 - KIT DESIGN CPLD W/BATT HOLDER
Lead Free Status / RoHS StatusLead free / RoHS CompliantFeatures-
Number Of Logic Elements/cells-Other names122-1388
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DS054 (v2.5) May 22, 2009
Features
Optimized for high-performance 3.3V systems
-
5 ns pin-to-pin logic delays, with internal system
frequency up to 208 MHz
-
Small footprint packages including VQFPs, TQFPs
and CSPs (Chip Scale Package)
-
Pb-free available for all packages
-
Lower power operation
-
5V tolerant I/O pins accept 5V, 3.3V, and 2.5V
signals
-
3.3V or 2.5V output capability
-
Advanced 0.35 micron feature size CMOS
FastFLASH technology
Advanced system features
-
In-system programmable
-
Superior pin-locking and routability with
FastCONNECT II switch matrix
-
Extra wide 54-input Function Blocks
-
Up to 90 product-terms per macrocell with
individual product-term allocation
Table 1: XC9500XL Device Family
Macrocells
Usable Gates
Registers
T
(ns)
PD
T
(ns)
SU
T
(ns)
CO
f
(MHz)
SYSTEM
© 1998–2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other
countries. All other trademarks are the property of their respective owners.
DS054 (v2.5) May 22, 2009
Product Specification
0
XC9500XL High-Performance CPLD
Family Data Sheet
Product Specification
0
0
-
Local clock inversion with three global and one
product-term clocks
-
Individual output enable per output pin with local
inversion
-
Input hysteresis on all user and boundary-scan pin
inputs
-
Bus-hold circuitry on all user pin inputs
-
Supports hot-plugging capability
-
Full IEEE Std 1149.1 boundary-scan (JTAG)
support on all devices
Four pin-compatible device densities
-
36 to 288 macrocells, with 800 to 6400 usable
gates
Fast concurrent programming
Slew rate control on individual outputs
Enhanced data security features
Excellent quality and reliability
-
10,000 program/erase cycles endurance rating
-
20 year data retention
Pin-compatible with 5V core XC9500 family in common
package footprints
XC9536XL
XC9572XL
36
72
800
1,600
36
72
5
5
3.7
3.7
3.5
3.5
178
178
www.xilinx.com
XC95144XL
XC95288XL
144
288
3,200
6,400
144
288
5
6
3.7
4.0
3.5
3.8
178
208
1

XC9572XL-10VQG64C Summary of contents

  • Page 1

    ... Slew rate control on individual outputs • Enhanced data security features • Excellent quality and reliability - 10,000 program/erase cycles endurance rating - 20 year data retention • Pin-compatible with 5V core XC9500 family in common package footprints XC9536XL XC9572XL 36 72 800 1,600 3.7 3.7 3.5 3.5 ...

  • Page 2

    ... CSG48 VQ64 VQG64 TQ100 TQG100 CS144 CSG144 TQ144 TQG144 PQ208 PQG208 BG256 BGG256 FG256 FGG256 CS280 CSG280 Notes: 1. The letter "G" as the third character indicates a Pb-free package. DS054 (v2.5) May 22, 2009 Product Specification XC9500XL High-Performance CPLD Family Data Sheet XC9536XL XC9572XL ...

  • Page 3

    R 3 JTAG Port I/O I/O I/O I/O I/O I/O I/O I/O 3 I/O/GCK 1 I/O/GSR I/O/GTS Note: Function block outputs (indicated by the bold lines) drive the I/O blocks directly. Family Overview The FastFLASH XC9500XL family ...

  • Page 4

    R operation. The XC9500XL device exhibits symmetric full 3.3V output voltage swing to allow balanced rise and fall times. Additional details can be found in the application notes listed in "Further Reading" on page Architecture Description Each XC9500XL device is ...

  • Page 5

    R 54 Product Allocator Figure 3: XC9500XL Macrocell Within Function Block All global control signals are available to each individual macrocell, including clock, set/reset, and output enable sig- nals. As shown in Figure 4, the macrocell register clock originates from ...

  • Page 6

    R I/O/GSR I/O/GCK1 I/O/GCK2 I/O/GCK3 Figure 4: Macrocell Clock and Set/Reset Capability DS054 (v2.5) May 22, 2009 Product Specification XC9500XL High-Performance CPLD Family Data Sheet Product Term Set Product Term Clock Product Term Reset Global Set/Reset Global Clock 1 Global ...

  • Page 7

    R Product Term Allocator The product term allocator controls how the five direct prod- uct terms are assigned to each macrocell. For example, all five direct terms can drive the OR function as shown in Figure 5. Product Term Allocator ...

  • Page 8

    R The product term allocator can re-assign product terms from any macrocell within the FB by combining partial sums of products over several macrocells, as shown in In this example, the incremental delay is only 2 product terms are available ...

  • Page 9

    R The internal logic of the product term allocator is shown in Figure 8. From Upper Macrocell From Lower Macrocell DS054 (v2.5) May 22, 2009 Product Specification XC9500XL High-Performance CPLD Family Data Sheet To Upper Macrocell Product Term Allocator To ...

  • Page 10

    R FastCONNECT II Switch Matrix The FastCONNECT II Switch Matrix connects signals to the FB inputs, as shown in Figure 9. All IOB outputs (corre- FastCONNECT II Switch Matrix DS054 (v2.5) May 22, 2009 Product Specification XC9500XL High-Performance CPLD Family ...

  • Page 11

    R I/O Block The I/O Block (IOB) interfaces between the internal logic and the device user I/O pins. Each IOB includes an input To FastCONNECT Switch Matrix Macrocell (Inversion in AND-array) Product Term OE I/O/GTS1 I/O/GTS2 I/O/GTS3 I/O/GTS4 Figure 10: ...

  • Page 12

    R Each output driver is designed to provide fast switching with minimal power noise. All output drivers in the device may be configured for driving either 3.3V CMOS levels (which are compatible with 5V TTL levels as well) or 2.5V ...

  • Page 13

    R The XC9500XL architecture provides for superior pin-lock- ing characteristics with a combination of large number of routing switches in the FastCONNECT II switch matrix, a 54-wide input Function Block, and flexible, bidirectional product term allocation within each macrocell. These ...

  • Page 14

    R instructions are supported in each device. Additional instructions are included for in-system programming opera- tions. Design Security XC9500XL devices incorporate advanced data security fea- tures which fully protect the programming data against unauthorized reading or inadvertent device erasure/repro- gramming. ...

  • Page 15

    R Detailed timing information may be derived from the full tim- ing model shown in Figure 16. The values and explanations Combinatorial Logic Propagation Delay = T (a) T PSU Combinatorial Logic P-Term Clock Path Setup Time = T PSU ...

  • Page 16

    R Power-Up Characteristics During power-up, the XC9500XL device I/Os may be unde- fined until V rises above 1 Volt. This time period is CCINT called the subthreshold region, as transistors have not yet fully turned on powered ...

  • Page 17

    R Further Reading Further information on the XC9500XL CPLD family can be found at: http://www.xilinx.com/support/documentation/xc9500xl.htm. This site includes: • Pinouts contained in the density-specific data sheets • Package electrical and thermal characteristics in UG112, Device Package User Guide • Termination, ...

  • Page 18

    R Notice of Disclaimer THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND CONDITIONS OF http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT ...