IC MAX 3000A CPLD 64 100-TQFP

EPM3064ATC100-10N

Manufacturer Part NumberEPM3064ATC100-10N
DescriptionIC MAX 3000A CPLD 64 100-TQFP
ManufacturerAltera
SeriesMAX® 3000A
EPM3064ATC100-10N datasheet
 

Specifications of EPM3064ATC100-10N

Programmable TypeIn System ProgrammableDelay Time Tpd(1) Max10.0ns
Voltage Supply - Internal3 V ~ 3.6 VNumber Of Logic Elements/blocks4
Number Of Macrocells64Number Of Gates1250
Number Of I /o66Operating Temperature0°C ~ 85°C
Mounting TypeSurface MountPackage / Case100-TQFP, 100-VQFP
Voltage3.0 V ~ 3.6 VMemory TypeEEPROM
Number Of Logic Elements/cells4Lead Free Status / RoHS StatusLead free / RoHS Compliant
Features-Other names544-1974
EPM3064ATC100-10N
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MAX 3000A Programmable Logic Device Family Data Sheet
Figure 5. MAX 3000A PIA Routing
To LAB
PIA Signals
While the routing delays of channel–based routing schemes in masked or
FPGAs are cumulative, variable, and path–dependent, the MAX 3000A
PIA has a predictable delay. The PIA makes a design’s timing
performance easy to predict.
I/O Control Blocks
The I/O control block allows each I/O pin to be individually configured
for input, output, or bidirectional operation. All I/O pins have a tri–state
buffer that is individually controlled by one of the global output enable
signals or directly connected to ground or V
.
Figure 6
shows the I/O
CC
control block for MAX 3000A devices. The I/O control block has 6 or
10 global output enable signals that are driven by the true or complement
of two output enable signals, a subset of the I/O pins, or a subset of the
I/O macrocells.
Altera Corporation
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