IC MAX 3000A CPLD 64 100-TQFP

EPM3064ATC100-10N

Manufacturer Part NumberEPM3064ATC100-10N
DescriptionIC MAX 3000A CPLD 64 100-TQFP
ManufacturerAltera
SeriesMAX® 3000A
EPM3064ATC100-10N datasheet
 

Specifications of EPM3064ATC100-10N

Programmable TypeIn System ProgrammableDelay Time Tpd(1) Max10.0ns
Voltage Supply - Internal3 V ~ 3.6 VNumber Of Logic Elements/blocks4
Number Of Macrocells64Number Of Gates1250
Number Of I /o66Operating Temperature0°C ~ 85°C
Mounting TypeSurface MountPackage / Case100-TQFP, 100-VQFP
Voltage3.0 V ~ 3.6 VMemory TypeEEPROM
Number Of Logic Elements/cells4Lead Free Status / RoHS StatusLead free / RoHS Compliant
Features-Other names544-1974
EPM3064ATC100-10N
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Programming
MAX 3000A devices can be programmed on Windows–based PCs with an
Altera Logic Programmer card, MPU, and the appropriate device adapter.
with External
The MPU performs continuity checking to ensure adequate electrical
contact between the adapter and the device.
Hardware
f
For more information, see the
The Altera software can use text– or waveform–format test vectors created
with the Altera Text Editor or Waveform Editor to test the programmed
device. For added design verification, designers can perform functional
testing to compare the functional device behavior with the results of
simulation.
Data I/O, BP Microsystems, and other programming hardware
manufacturers also provide programming support for Altera devices.
f
For more information, see
IEEE Std.
MAX 3000A devices include the JTAG BST circuitry defined by IEEE
Std. 1149.1–1990.
1149.1 (JTAG)
MAX 3000A devices. The pin-out tables found on the Altera web site
(http://www.altera.com) or the Altera Digital Library show the location of
Boundary–Scan
the JTAG control pins for each device. If the JTAG interface is not
Support
required, the JTAG pins are available as user I/O pins.
Table 7. MAX 3000A JTAG Instructions
JTAG Instruction
SAMPLE/PRELOAD
Allows a snapshot of signals at the device pins to be captured and examined during
normal device operation, and permits an initial data pattern output at the device pins
EXTEST
Allows the external circuitry and board–level interconnections to be tested by forcing a
test pattern at the output pins and capturing test results at the input pins
BYPASS
Places the 1–bit bypass register between the TDI and TDO pins, which allows the BST
data to pass synchronously through a selected device to adjacent devices during normal
device operation
IDCODE
Selects the IDCODE register and places it between the TDI and TDO pins, allowing the
IDCODE to be serially shifted out of TDO
USERCODE
Selects the 32–bit USERCODE register and places it between the TDI and TDO pins,
allowing the USERCODE value to be shifted out of TDO
ISP Instructions
These instructions are used when programming MAX 3000A devices via the JTAG ports
with the MasterBlaster, ByteBlasterMV, or BitBlaster cable, or when using a Jam STAPL
file, JBC file, or SVF file via an embedded processor or test equipment
Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Altera Programming Hardware Data
Programming Hardware
Table 7
describes the JTAG instructions supported by
Description
Sheet.
Manufacturers.
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