IC MAX 3000A CPLD 64 100-TQFP

EPM3064ATC100-10N

Manufacturer Part NumberEPM3064ATC100-10N
DescriptionIC MAX 3000A CPLD 64 100-TQFP
ManufacturerAltera
SeriesMAX® 3000A
EPM3064ATC100-10N datasheet
 


Specifications of EPM3064ATC100-10N

Programmable TypeIn System ProgrammableDelay Time Tpd(1) Max10.0ns
Voltage Supply - Internal3 V ~ 3.6 VNumber Of Logic Elements/blocks4
Number Of Macrocells64Number Of Gates1250
Number Of I /o66Operating Temperature0°C ~ 85°C
Mounting TypeSurface MountPackage / Case100-TQFP, 100-VQFP
Voltage3.0 V ~ 3.6 VMemory TypeEEPROM
Number Of Logic Elements/cells4Lead Free Status / RoHS StatusLead free / RoHS Compliant
Features-Other names544-1974
EPM3064ATC100-10N
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MAX 3000A Programmable Logic Device Family Data Sheet
Macrocells
MAX 3000A macrocells can be individually configured for either
sequential or combinatorial logic operation. Macrocells consist of three
functional blocks: logic array, product–term select matrix, and
programmable register.
Figure 2. MAX 3000A Macrocell
LAB Local Array
36 Signals
16 Expander
from PIA
Product Terms
Combinatorial logic is implemented in the logic array, which provides
five product terms per macrocell. The product–term select matrix
allocates these product terms for use as either primary logic inputs (to the
OR and XOR gates) to implement combinatorial functions, or as secondary
inputs to the macrocell’s register preset, clock, and clock enable control
functions.
Two kinds of expander product terms (“expanders”) are available to
supplement macrocell logic resources:
The Altera development system automatically optimizes product–term
allocation according to the logic requirements of the design.
6
Figure 2
Global
Clear
Parallel Logic
Expanders
(from other
macrocells)
Product-
Term
Select
Matrix
Clear
Select
Shared Logic
Expanders
Shareable expanders, which are inverted product terms that are fed
back into the logic array
Parallel expanders, which are product terms borrowed from adjacent
macrocells
shows a MAX 3000A macrocell.
Global
Clocks
2
Programmable
Register
Register
Bypass
PRN
D/T
Q
Clock/
Enable
ENA
CLRN
Select
VCC
To PIA
Altera Corporation
To I/O
Control
Block