EPM3064ATC100-4N Altera, EPM3064ATC100-4N Datasheet - Page 4

• Manufacturer Part Number: EPM3064ATC100-4N
• Description: IC MAX 3000A CPLD 64 100-TQFP
• Manufacturer: Altera
• Series: MAX® 3000Ar

Specifications of EPM3064ATC100-4N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 4.5ns
• Voltage Supply - Internal: 3 V ~ 3.6 V
• Number Of Logic Elements/blocks: 4
• Number Of Macrocells: 64
• Number Of Gates: 1250
• Number Of I /o: 66
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Voltage: 3.0 V ~ 3.6 V
• Memory Type: EEPROM
• Number Of Logic Elements/cells: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 544-1975; EPM3064ATC100-4N

MAX 3000A Programmable Logic Device Family Data Sheet
Functional
Description
4
f
MAX 3000A devices contain 32 to 512 macrocells, combined into groups
of 16 macrocells called logic array blocks (LABs). Each macrocell has a
programmable–AND/fixed–OR array and a configurable register with
independently programmable clock, clock enable, clear, and preset
functions. To build complex logic functions, each macrocell can be
supplemented with shareable expander and high–speed parallel
expander product terms to provide up to 32 product terms per macrocell.
MAX 3000A devices provide programmable speed/power optimization.
Speed–critical portions of a design can run at high speed/full power,
while the remaining portions run at reduced speed/low power. This
speed/power optimization feature enables the designer to configure one
or more macrocells to operate at 50% or lower power while adding only a
nominal timing delay. MAX 3000A devices also provide an option that
reduces the slew rate of the output buffers, minimizing noise transients
when non–speed–critical signals are switching. The output drivers of all
MAX 3000A devices can be set for 2.5 V or 3.3 V, and all input pins are
2.5–V, 3.3–V, and 5.0-V tolerant, allowing MAX 3000A devices to be used
in mixed–voltage systems.
MAX 3000A devices are supported by Altera development systems,
which are integrated packages that offer schematic, text—including
VHDL, Verilog HDL, and the Altera Hardware Description Language
(AHDL)—and waveform design entry, compilation and logic synthesis,
simulation and timing analysis, and device programming. The software
provides EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other
interfaces for additional design entry and simulation support from other
industry–standard PC– and UNIX–workstation–based EDA tools. The
software runs on Windows–based PCs, as well as Sun SPARCstation, and
HP 9000 Series 700/800 workstations.
For more information on development tools, see the
Programmable Logic Development System & Software Data Sheet
Quartus Programmable Logic Development System & Software Data
The MAX 3000A architecture includes the following elements:
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■
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The MAX 3000A architecture includes four dedicated inputs that can be
used as general–purpose inputs or as high–speed, global control signals
(clock, clear, and two output enable signals) for each macrocell and I/O
pin.
Figure 1
Logic array blocks (LABs)
Macrocells
Expander product terms (shareable and parallel)
Programmable interconnect array (PIA)
I/O control blocks
shows the architecture of MAX 3000A devices.
MAX+PLUS II
Altera Corporation
and the
Sheet.