IC MAX II CPLD 240 LE 100-TQFP

EPM240T100C5N

Manufacturer Part NumberEPM240T100C5N
DescriptionIC MAX II CPLD 240 LE 100-TQFP
ManufacturerAltera
SeriesMAX® II
EPM240T100C5N datasheets
 


Specifications of EPM240T100C5N

Programmable TypeIn System ProgrammableDelay Time Tpd(1) Max4.7ns
Voltage Supply - Internal2.5V, 3.3VNumber Of Logic Elements/blocks240
Number Of Macrocells192Number Of I /o80
Operating Temperature0°C ~ 85°CMounting TypeSurface Mount
Package / Case100-TQFP, 100-VQFPVoltage2.5V, 3.3V
Memory TypeFLASHNumber Of Logic Elements/cells240
Lead Free Status / RoHS StatusLead free / RoHS CompliantFeatures-
Other names544-1964
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MII51001-1.9
Introduction
The MAX
II family of instant-on, non-volatile CPLDs is based on a 0.18-µm,
®
6-layer-metal-flash process, with densities from 240 to 2,210 logic elements (LEs) (128
to 2,210 equivalent macrocells) and non-volatile storage of 8 Kbits. MAX II devices
offer high I/O counts, fast performance, and reliable fitting versus other CPLD
architectures. Featuring MultiVolt core, a user flash memory (UFM) block, and
enhanced in-system programmability (ISP), MAX II devices are designed to reduce
cost and power while providing programmable solutions for applications such as bus
bridging, I/O expansion, power-on reset (POR) and sequencing control, and device
configuration control.
Features
The MAX II CPLD has the following features:
Low-cost, low-power CPLD
Instant-on, non-volatile architecture
Standby current as low as 25 µA
Provides fast propagation delay and clock-to-output times
Provides four global clocks with two clocks available per logic array block (LAB)
UFM block up to 8 Kbits for non-volatile storage
MultiVolt core enabling external supply voltages to the device of either
3.3 V/2.5 V or 1.8 V
MultiVolt I/O interface supporting 3.3-V, 2.5-V, 1.8-V, and 1.5-V logic levels
Bus-friendly architecture including programmable slew rate, drive strength,
bus-hold, and programmable pull-up resistors
Schmitt triggers enabling noise tolerant inputs (programmable per pin)
I/Os are fully compliant with the Peripheral Component Interconnect Special
Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 3.3-V
operation at 66 MHz
Supports hot-socketing
Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry
compliant with IEEE Std. 1149.1-1990
ISP circuitry compliant with IEEE Std. 1532
© August 2009 Altera Corporation
1. Introduction
MAX II Device Handbook

EPM240T100C5N Summary of contents

  • Page 1

    ... Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 3.3-V operation at 66 MHz Supports hot-socketing ■ Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry ■ compliant with IEEE Std. 1149.1-1990 ■ ISP circuitry compliant with IEEE Std. 1532 © August 2009 Altera Corporation 1. Introduction MAX II Device Handbook ...

  • Page 2

    ... MAX II Logic Element to DC and Switching –6 –7 –8 — — — — — — — — — — — — © August 2009 Altera Corporation ...

  • Page 3

    ... Micro FineLine FineLine Package BGA BGA Pitch (mm) 0.5 0.5 Area (mm2 Length × width 5 × × 6 (mm × mm) © August 2009 Altera Corporation II software can automatically cross-reference ® 144-Pin 100-Pin Micro FineLine 100-Pin 144-Pin FineLine BGA TQFP TQFP BGA 80 80 — ...

  • Page 4

    ... Updated document with MAX IIZ information. Chapter 1: Introduction Referenced Documents EPM240G EPM570G EPM1270G EPM2210G EPM240Z EPM570Z (1) 1.8 V 1.5 V, 1.8 V, 2.5 V, 3.3 V external supply powers the device core directly. white paper Summary of Changes — — — — © August 2009 Altera Corporation ...

  • Page 5

    ... Updated timing numbers in Table 1-1. ■ version 1.3 December 2004, Updated timing numbers in Table 1-1. ■ version 1.2 June 2004, Updated timing numbers in Table 1-1. ■ version 1.1 © August 2009 Altera Corporation Changes Made 1–5 Summary of Changes — — — MAX II Device Handbook ...

  • Page 6

    ... MAX II Device Handbook Chapter 1: Introduction Document Revision History © August 2009 Altera Corporation ...