IC MAX 7000 CPLD 64 44-TQFP

EPM7064STC44-10N

Manufacturer Part NumberEPM7064STC44-10N
DescriptionIC MAX 7000 CPLD 64 44-TQFP
ManufacturerAltera
SeriesMAX® 7000
EPM7064STC44-10N datasheet
 


Specifications of EPM7064STC44-10N

Programmable TypeIn System ProgrammableDelay Time Tpd(1) Max10.0ns
Voltage Supply - Internal4.75 V ~ 5.25 VNumber Of Logic Elements/blocks4
Number Of Macrocells64Number Of Gates1250
Number Of I /o36Operating Temperature0°C ~ 70°C
Mounting TypeSurface MountPackage / Case44-TQFP, 44-VQFP
Voltage5VMemory TypeEEPROM
Number Of Logic Elements/cells4Lead Free Status / RoHS StatusLead free / RoHS Compliant
Features-Other names544-2020
EPM7064STC44-10N
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MAX 7000 Programmable Logic Device Family Data Sheet
Figure 4
Figure 4. MAX 7000E & MAX 7000S Device Macrocell
Logic Array
36 Signals
16 Expander
from PIA
Product Terms
Combinatorial logic is implemented in the logic array, which provides
five product terms per macrocell. The product-term select matrix allocates
these product terms for use as either primary logic inputs (to the OR and
XOR gates) to implement combinatorial functions, or as secondary inputs
to the macrocell’s register clear, preset, clock, and clock enable control
functions. Two kinds of expander product terms (“expanders”) are
available to supplement macrocell logic resources:
The Altera development system automatically optimizes product-term
allocation according to the logic requirements of the design.
For registered functions, each macrocell flipflop can be individually
programmed to implement D, T, JK, or SR operation with programmable
clock control. The flipflop can be bypassed for combinatorial operation.
During design entry, the designer specifies the desired flipflop type; the
Altera development software then selects the most efficient flipflop
operation for each registered function to optimize resource utilization.
10
shows a MAX 7000E and MAX 7000S device macrocell.
Global
Global
Clear
Clocks
2
Parallel Logic
Expanders
(from other
macrocells)
Product-
Term
Select
Matrix
Clear
Select
Shared Logic
Expanders
Shareable expanders, which are inverted product terms that are fed
back into the logic array
Parallel expanders, which are product terms borrowed from adjacent
macrocells
Fast Input
Programmable
Select
Register
Register
Bypass
PRN
D/T
Q
Clock/
Enable
ENA
CLRN
Select
VCC
to PIA
Altera Corporation
from
I/O pin
to I/O
Control
Block