EPM7064SLC44-7 Altera, EPM7064SLC44-7 Datasheet - Page 24

IC MAX 7000 CPLD 64 44-PLCC

EPM7064SLC44-7

Manufacturer Part Number
EPM7064SLC44-7
Description
IC MAX 7000 CPLD 64 44-PLCC
Manufacturer
Altera
Series
MAX® 7000r
Datasheet

Specifications of EPM7064SLC44-7

Programmable Type
In System Programmable
Delay Time Tpd(1) Max
7.5ns
Voltage Supply - Internal
4.75 V ~ 5.25 V
Number Of Logic Elements/blocks
4
Number Of Macrocells
64
Number Of Gates
1250
Number Of I /o
36
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
44-PLCC
Voltage
5V
Memory Type
EEPROM
Number Of Logic Elements/cells
4
Family Name
MAX 7000S
# Macrocells
64
Number Of Usable Gates
1250
Frequency (max)
166.7MHz
Propagation Delay Time
7.5ns
Number Of Logic Blocks/elements
4
# I/os (max)
36
Operating Supply Voltage (typ)
5V
In System Programmable
Yes
Operating Supply Voltage (min)
4.75V
Operating Supply Voltage (max)
5.25V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
44
Package Type
PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1196-5

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MAX 7000 Programmable Logic Device Family Data Sheet
24
f
Figure 9
Figure 9. MAX 7000 JTAG Waveforms
Table 12
devices.
For more information, see
Boundary-Scan Testing in Altera
Captured
Symbol
Table 12. JTAG Timing Parameters & Values for MAX 7000S Devices
t
t
t
t
t
t
t
t
t
t
t
t
t
JCP
JCH
JCL
JPSU
JPH
JPCO
JPZX
JPXZ
JSSU
JSH
JSCO
JSZX
JSXZ
Driven
Signal
Signal
to Be
to Be
TMS
TDO
TCK
TDI
shows the timing requirements for the JTAG signals.
shows the JTAG timing parameters and values for MAX 7000S
TCK clock period
TCK clock high time
TCK clock low time
JTAG port setup time
JTAG port hold time
JTAG port clock to output
JTAG port high impedance to valid output
JTAG port valid output to high impedance
Capture register setup time
Capture register hold time
Update register clock to output
Update register high impedance to valid output
Update register valid output to high impedance
t
JCH
t
t
JPZX
JSZX
t
JCP
t
JSSU
t
JCL
Parameter
Application Note 39 (IEEE 1149.1 (JTAG)
t
Devices).
JSH
t
t
JPCO
JSCO
t
JPSU
t
t
JSXZ
JPH
Altera Corporation
100
Min
50
50
20
45
20
45
t
Max
JPXZ
25
25
25
25
25
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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