EPM7064SLC44-7 Altera, EPM7064SLC44-7 Datasheet - Page 32

IC MAX 7000 CPLD 64 44-PLCC

EPM7064SLC44-7

Manufacturer Part Number
EPM7064SLC44-7
Description
IC MAX 7000 CPLD 64 44-PLCC
Manufacturer
Altera
Series
MAX® 7000r
Datasheet

Specifications of EPM7064SLC44-7

Programmable Type
In System Programmable
Delay Time Tpd(1) Max
7.5ns
Voltage Supply - Internal
4.75 V ~ 5.25 V
Number Of Logic Elements/blocks
4
Number Of Macrocells
64
Number Of Gates
1250
Number Of I /o
36
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
44-PLCC
Voltage
5V
Memory Type
EEPROM
Number Of Logic Elements/cells
4
Family Name
MAX 7000S
# Macrocells
64
Number Of Usable Gates
1250
Frequency (max)
166.7MHz
Propagation Delay Time
7.5ns
Number Of Logic Blocks/elements
4
# I/os (max)
36
Operating Supply Voltage (typ)
5V
In System Programmable
Yes
Operating Supply Voltage (min)
4.75V
Operating Supply Voltage (max)
5.25V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
44
Package Type
PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1196-5

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MAX 7000 Programmable Logic Device Family Data Sheet
32
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
IN
IO
FIN
SEXP
PEXP
LAD
LAC
IOE
OD1
OD2
OD3
ZX1
ZX2
ZX3
XZ
SU
H
FSU
FH
RD
COMB
IC
EN
GLOB
PRE
CLR
PIA
LPA
Table 20. MAX 7000 & MAX 7000E Internal Timing Parameters
Symbol
Input pad and buffer delay
I/O input pad and buffer delay
Fast input delay
Shared expander delay
Parallel expander delay
Logic array delay
Logic control array delay
Internal output enable delay
Output buffer and pad delay
Slow slew rate = off, V
Output buffer and pad delay
Slow slew rate = off, V
Output buffer and pad delay
Slow slew rate = on,
V
Output buffer enable delay
Slow slew rate = off, V
Output buffer enable delay
Slow slew rate = off, V
Output buffer enable delay
Slow slew rate = on
V
Output buffer disable delay
Register setup time
Register hold time
Register setup time of fast input
Register hold time of fast input
Register delay
Combinatorial delay
Array clock delay
Register enable time
Global control delay
Register preset time
Register clear time
PIA delay
Low-power adder
CCIO
CCIO
= 5.0 V or 3.3 V
= 5.0 V or 3.3 V
Parameter
CCIO
CCIO
CCIO
CCIO
= 5.0 V
= 3.3 V
= 5.0 V
= 3.3 V
(2)
(2)
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 5 pF
(2)
(2)
(8)
Conditions
(7)
(2)
(7)
(2)
Speed Grade -6
Min
3.0
1.5
2.5
0.5
Note (1)
Max
10.0
0.4
0.4
0.8
3.5
0.8
2.0
2.0
2.0
2.5
7.0
4.0
4.5
9.0
4.0
0.8
0.8
2.5
2.0
0.8
2.0
2.0
0.8
Speed Grade -7
Min
3.0
2.0
3.0
0.5
Altera Corporation
10.0
Max
0.5
0.5
1.0
4.0
0.8
3.0
3.0
2.0
2.0
2.5
7.0
4.0
4.5
9.0
4.0
1.0
1.0
3.0
3.0
1.0
2.0
2.0
1.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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